FinFET Source/Drain Doping for Low-Resistance Deep pn Junctions
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in reducing channel resistance and parasitic resistance in FinFET devices, while also minimizing dopant diffusion and P4V cluster formation in source/drain regions, which affects device performance and integration density.
Innovation Solution
The implementation of a high energy/low dose implantation process for epitaxially grown semiconductor materials in FinFET devices, allowing for reduced channel resistance, controlled dopant activation, and the formation of deep diffusion-less pn junctions between source/drain and channel regions, thereby improving device performance and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional implantation processes are used to reduce channel resistance, then dopant diffusion increases and P4V clusters form, but if implantation dose is reduced to minimize diffusion and cluster formation, then channel resistance increases
Solution Approach 1:
The patent applies parameter changes by using high energy (e.g., 1 MeV) and low dose (e.g., 1E13 to 1E15 atoms/cm²) implantation conditions. This changes the implantation parameters from conventional high-dose/low-energy to low-dose/high-energy, achieving deep dopant penetration with minimal diffusion and reduced P4V cluster formation while maintaining low channel resistance
Solution Approach 2:
The patent transitions from conventional two-dimensional implantation (surface-level) to deep three-dimensional dopant distribution. By using high energy implantation, dopants are distributed deep into the source/drain regions (e.g., 50-200 nm depth), creating a vertical concentration gradient that reduces channel resistance without excessive lateral diffusion
2Productivity
If integration density is increased by reducing minimum feature size, then more components can be integrated, but manufacturing precision and control of dopant profiles become more difficult
Solution Approach 1:
The patent uses high energy implantation parameters to achieve precise dopant depth control. The high energy (1 MeV) allows dopants to penetrate to specific depths (50-200 nm) with controlled distribution, enabling accurate dopant profiling even as feature sizes are reduced for higher integration density
Solution Approach 2:
The patent performs preliminary high energy/low dose implantation before final dopant activation. This preliminary action creates a deep dopant distribution pattern that guides subsequent processing steps, ensuring precise dopant profiles are established early in the manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces channel resistance and parasitic resistance, minimizes dopant diffusion, and enhances dopant activation, leading to improved device performance and integration density by accurately defining pn junctions and modulating dopant profiles.
Implementation Method 1
an implantation process is performed on the epitaxial semiconductor material. The implantation process includes implanting first implants into the epitaxial semiconductor material and implanting second implants into the epitaxial semiconductor material
Implementation Method 2
an anneal process is performed on the epitaxial semiconductor material. The anneal process forms a doped region in the semiconductor fin at an interface between the epitaxial semiconductor material and the semiconductor fin
Data Source
AI summary
A semiconductor device and a method of forming the same are provided. The method includes forming a semiconductor fin extending from a substrate. A dummy gate stack is formed over the semiconductor fin. The dummy gate stack extends along sidewalls and a top surface of the semiconductor fin. The semiconductor fin is patterned to form a recess in the semiconductor fin. A semiconductor material is deposited in the recess. An implantation process is performed on the semiconductor material. The implantation process includes implanting first implants into the semiconductor material and implanting second implants into the semiconductor material. The first implants have a first implantation energy. The second implants have a second implantation energy different from the first implantation energy.