FinFET Source/Drain Epitaxial Structures for Gate Length Reduction
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Solution Overview
Problem
Existing semiconductor device fabrication methods face challenges in achieving effective gate length reduction and power efficiency, particularly in FinFETs, due to limitations in gate stack formation and source/drain epitaxial structure design.
Innovation Solution
The method involves forming semiconductor devices with vertex structures for gate, source, and drain regions, using epitaxial growth of semiconductor materials like silicon germanium and gallium arsenide, and implementing a superlattice structure in source/drain regions to enhance channel mobility and reduce tunneling barriers, allowing for smaller gate lengths and lower voltage thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional fabrication methods are used for FinFETs, then manufacturing process is simpler, but gate length reduction is limited and power efficiency deteriorates
Solution Approach 1:
The source/drain structure is segmented into multiple epitaxial layers with different semiconductor materials (e.g., SiGe, Si, GaAs) and doping concentrations. This segmentation allows each layer to contribute differently to carrier transport, enabling effective gate length reduction while maintaining power efficiency through optimized carrier injection and transport in each segment
Solution Approach 2:
Different regions of the source/drain structure have locally optimized properties: undoped or lightly-doped regions near the channel for carrier injection, heavily-doped regions for low resistance contact, and intermediate regions with graded composition for carrier transport. This local quality optimization resolves the contradiction by allowing gate length reduction without compromising power efficiency
2Length of moving object
If gate stack formation is simplified, then manufacturing is easier, but effective gate length reduction is constrained
Solution Approach 1:
Source/drain epitaxial structures are formed preliminary to gate stack formation, with pre-defined vertex structures and material compositions. This preliminary action enables subsequent gate stack formation to achieve effective gate length reduction without requiring complex in-situ modifications during gate fabrication
Solution Approach 2:
The source/drain structures extend into the third dimension with vertex configurations that protrude toward the gate. This dimensional approach allows effective gate length reduction by utilizing vertical and lateral extensions rather than solely reducing horizontal gate dimensions, simplifying the gate stack formation process
3Speed
If source/drain epitaxial structure is optimized for carrier transport, then channel mobility improves, but manufacturing complexity increases
Solution Approach 1:
The epitaxial structure uses systematic parameter changes including graded semiconductor composition (e.g., SiGe to Si ratio), progressive doping concentration changes, and controlled layer thickness variations. These parameter changes improve channel mobility through strain engineering and carrier concentration optimization while maintaining manufacturability through standardized epitaxial growth processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of semiconductor devices with improved power efficiency, reduced voltage thresholds, and lower power consumption by optimizing the channel materials and structure, facilitating the development of advanced transistors like FinFETs.
Implementation Method 1
using epitaxial growth of semiconductor materials like silicon germanium and gallium arsenide
Data Source
AI summary
A method for fabricating a semiconductor device includes providing a first wafer comprising a substrate and a first semiconductor material layer, bonding the first wafer to a second wafer, the second wafer comprising a sacrificial layer and a second semiconductor material layer, removing the sacrificial layer, patterning the bonded wafers to create a first structure and a second structure, removing the second semiconductor material from the first structure, forming a first type of transistor in the first semiconductor material of the first structure, and forming a second type of transistor in the second semiconductor material of the second structure.