FinFET Source Drain Resistance Reduction via Epitaxial Regrowth
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
FinFETs face challenges in achieving reduced resistance at source and drain junctions due to limited thermal budgets during epitaxial regrowth, which results in inadequately doped regions and increased resistance.
Innovation Solution
Forming reduced resistance regions by removing portions of the source and drain regions and replacing them with a semiconductor composition having a higher conductivity dopant concentration, such as InAs, and using epitaxial growth to create highly doped epitaxial regions with doping levels between 10^18 and 10^21 dopants/cm^3, along with forming gate spacers from low-k dielectrics to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If epitaxial regrowth is used to form source and drain regions, then the fin structure can be formed with III-V semiconductor materials, but the thermal budget limitations result in inadequately doped regions with high resistance
Solution Approach 1:
The patent changes the doping parameter by introducing a separate doping step after epitaxial regrowth. Instead of relying solely on in-situ doping during epitaxial growth (which is limited by thermal budget), the patent applies post-epitaxial doping to achieve the required dopant concentration (10^18 to 10^21 dopants/cm³) in the source and drain regions, thereby resolving the contradiction between material formation and doping precision.
2Reliability
If source and drain regions are heavily doped to reduce resistance, then conductivity improves, but parasitic capacitance increases due to closer junctions to the channel
Solution Approach 1:
The patent applies local quality by creating different doping concentrations in different regions. The source and drain regions are heavily doped (10^18 to 10^21 dopants/cm³) to reduce resistance, while the channel region maintains lower doping to minimize parasitic capacitance. This spatial differentiation of doping quality allows simultaneous optimization of conductivity and capacitance characteristics.
3Productivity
If the fin structure is scaled to smaller dimensions for higher density, then device density improves, but resistance at source and drain junctions increases
Solution Approach 1:
The patent applies preliminary action by performing epitaxial regrowth with intentional doping before final device formation. The source and drain regions are pre-doped during the epitaxial regrowth step, establishing a foundation for low resistance before subsequent processing steps. This preliminary doping action ensures that even as devices are scaled to smaller dimensions, the source and drain regions maintain adequate conductivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in finFETs with significantly reduced resistance in source and drain regions, enhancing conductivity and operational efficiency by precisely locating doped regions close to the channel, thereby improving switching speeds and reducing leakage current.
Implementation Method 1
forming gate spacers from low-k dielectrics to reduce parasitic capacitance
Data Source
AI summary
Methods and structures for forming a reduced resistance region of a finFET are described. According to some aspects, a dummy gate and first gate spacer may be formed above a fin comprising a first semiconductor composition. At least a portion of source and drain regions of the fin may be removed, and a second semiconductor composition may be formed in the source and drain regions in contact with the first semiconductor composition. A second gate spacer may be formed covering the first gate spacer. The methods may be used to form finFETs having reduced resistance at source and drain junctions.