FinFET Source/Drain Epitaxial Growth for Thermal Budget Constraints
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Solution Overview
Problem
The limited thermal budget in FinFET device manufacturing restricts the effectiveness of ion implant engineering in improving junction profiles and electrical performance, as high-temperature process operations are limited, hindering the optimization of source/drain regions.
Innovation Solution
A method involving forming a fin in a semiconductor substrate, creating a gate structure, and then defining a source/drain cavity through a series of etching processes, including anisotropic and isotropic etching, followed by an amorphization implant and further isotropic etching to create a unique stepped profile, and finally performing epitaxial growth to fill the cavity with semiconductor material, which enhances the source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ion implant engineering is used to improve junction profiles and electrical performance, then the electrical performance is improved, but the process requires high-temperature operations that exceed the limited thermal budget in FinFET manufacturing
Solution Approach 1:
The patent changes the material composition parameter by forming source/drain regions from silicon-germanium alloy material instead of using traditional ion implantation into silicon. This material substitution allows achieving improved junction profiles and electrical performance without requiring high-temperature annealing processes, thus resolving the contradiction between electrical performance improvement and thermal budget constraints.
Solution Approach 2:
The patent replaces the thermal/chemical process of ion implantation and high-temperature annealing with a mechanical/physical process of epitaxial growth. By using selective epitaxial growth to form silicon-germanium source/drain regions, the method achieves junction profile optimization without relying on high-temperature thermal processes, thereby substituting a thermal-based system with a growth-based system that operates within the thermal budget.
2Manufacturing precision
If traditional ion implantation and high-temperature annealing are used, then junction profiles can be optimized, but the process complexity and number of process steps increase
Solution Approach 1:
The patent merges multiple process steps into a more integrated flow. By forming the source/drain regions through epitaxial growth of silicon-germanium material in-situ, the method combines material deposition, doping, and junction formation into a single integrated process step, eliminating the need for separate ion implantation and high-temperature annealing steps, thus reducing overall process complexity while achieving optimized junction profiles.
Solution Approach 2:
The patent changes the fundamental approach to junction formation by using epitaxial growth parameters (temperature, pressure, gas composition, growth rate) instead of ion implantation parameters (ion energy, ion dose, annealing temperature). This parameter transformation enables achieving precise junction profile control through a different set of controllable parameters that are more compatible with FinFET manufacturing constraints and require fewer process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for improved junction profiles and increased drive current in FinFET devices by positioning the epitaxial semiconductor material more laterally inward, enhancing the electrical performance and exceeding the limitations of traditional thermal budgets.
Implementation Method 1
performing an epitaxial growth process to form an epi semiconductor material in the source/drain cavity
Implementation Method 2
forming a source/drain cavity by performing a first anisotropic etching process to define a first cavity in the fin
Implementation Method 3
performing a second isotropic etching process on the first cavity so as to define a second cavity in the fin
Implementation Method 4
performing an amorphization implant process to form a region of amorphous fin material in the fin at a bottom of the second cavity
Data Source
AI summary
One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate, forming a gate structure around the fin and, after forming the gate structure, forming a final source/drain cavity in the fin, wherein the source/drain cavity includes an upper innermost edge and a lower innermost edge, both of which extend laterally under at least a portion of the gate structure, and wherein the lower innermost edge extends laterally further under the gate structure than does the upper innermost edge. The method also includes performing an epitaxial growth process to form an epi semiconductor material in the final source/drain cavity.