FinFET Source/Drain Epitaxy Order for Dielectric Fin Defect Control

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Solution Overview

Problem

In the formation of Fin Field-Effect Transistors (FinFETs), the selective loss defect, where source/drain material adversely grows on dielectric material due to loss of selectivity, is challenging to address, especially for p-type FinFETs, as the available process gases are less effective in removing these defects compared to n-type defects.

Innovation Solution

The approach involves forming n-type source/drain regions before p-type regions, allowing for easier removal of n-type selective-loss defects during subsequent p-type epitaxy processes, utilizing specific process gases and masks to selectively grow semiconductor materials and manage defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If source/drain regions are formed by etching silicon fins to form recesses and then performing epitaxy process, then source/drain regions can be formed with proper material composition, but selective loss defects occur where source/drain material adversely grows on dielectric material

Engineering Contradiction:
Improveselectivity of epitaxy growthVSAvoidselective loss defects
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The patent segments the source/drain formation process into separate steps for different FinFET types (n-type and p-type). By forming n-type source/drain regions first, then forming p-type source/drain regions in a subsequent process, the patent can use different process gases optimized for each type, thereby improving selectivity and reducing selective loss defects for each material system

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the process gas parameters between n-type and p-type epitaxy processes. Specific process gases are selected for each epitaxy step to optimize growth selectivity and minimize adverse growth on dielectric materials, directly addressing the selectivity-defect tradeoff

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If separate processes are used for forming n-type and p-type source/drain regions, then material-specific optimization is achieved, but process complexity and time increase

Engineering Contradiction:
Improvematerial-specific formation precisionVSAvoidprocess flow complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent divides the source/drain formation into segmented processes for n-type and p-type regions, allowing each to be optimized for its specific material requirements while maintaining overall process control and reducing defects

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary formation of n-type source/drain regions before forming p-type regions. This preliminary action allows optimization of each step independently while establishing a foundation that simplifies subsequent processing

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method effectively reduces the occurrence and removal of selective-loss defects, particularly for p-type FinFETs, by forming n-type regions first, which simplifies the subsequent p-type epitaxy process and enhances the overall precision and efficiency of source/drain formation.

Implementation Method 1

performing an epitaxy process to grow epitaxy regions from the recesses

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS11855188B2Source/drain formation with reduced selective loss defects
Publication Date: 2023.12.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11855188B2 patent drawing
  • US11855188B2 patent drawing
  • US11855188B2 patent drawing

AI summary

A method includes forming a first semiconductor fin and a second semiconductor fin in an n-type Fin Field-Effect (FinFET) region and a p-type FinFET region, respectively, forming a first dielectric fin and a second dielectric fin in the n-type FinFET region and the p-type FinFET region, respectively, forming a first epitaxy mask to cover the second semiconductor fin and the second dielectric fin, performing a first epitaxy process to form an n-type epitaxy region based on the first semiconductor fin, removing the first epitaxy mask, forming a second epitaxy mask to cover the n-type epitaxy region and the first dielectric fin, performing a second epitaxy process to form a p-type epitaxy region based on the second semiconductor fin, and removing the second epitaxy mask. After the second epitaxy mask is removed, a portion of the second epitaxy mask is left on the first dielectric fin.