FinFET Source Drain Epitaxy Profile Control
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Solution Overview
Problem
Traditional cyclic deposition etch (CDE) processes for forming epitaxial source/drain features in FinFETs lack precise profile control, particularly at advanced technology nodes with fin spacing less than 25 nm, leading to large variations in lateral dimension and potential electrical shorts or damage during fabrication.
Innovation Solution
A method involving a single deposition and etching process using a silicon-containing precursor and a chlorine-containing precursor, with a flow rate ratio less than 5, to form merged epitaxial source and drain features that span the source and drain regions of adjacent fins, ensuring precise control over lateral growth and minimizing lateral dimension variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional cyclic deposition etch (CDE) processes are used to form epitaxial source/drain features, then the features can be formed in FinFET structures, but the lateral dimension varies significantly and electrical shorts or damage may occur
Solution Approach 1:
The patent changes the process parameters by using a single deposition and etching cycle instead of multiple cyclic cycles. The deposition process uses a silicon-containing precursor with a chlorine-containing precursor at a flow rate ratio less than 5, and the etching process uses the chlorine-containing precursor to modify the profile. This parameter change achieves precise lateral dimension control (within ±7 nm) while preventing electrical shorts, resolving the contradiction between manufacturing precision and reliability
Solution Approach 2:
The patent applies periodic action through the single deposition-etching cycle that alternates between depositing semiconductor material and etching to modify the profile. This periodic process within a single cycle achieves both precise lateral dimension control and reliable electrical isolation, eliminating the need for multiple CDE cycles that caused variation accumulation
2Productivity
If fin spacing is reduced to less than 25 nm for advanced technology nodes, then production efficiency increases and costs decrease, but controlling the profile and dimension of source/drain features becomes more difficult
Solution Approach 1:
The patent uses parameter changes by optimizing the flow rate ratio of silicon-containing precursor to chlorine-containing precursor (less than 5) and using a single deposition-etching cycle. This enables precise control of source/drain feature dimensions even at fin spacing less than 25 nm, maintaining manufacturing precision while enabling advanced technology nodes for higher productivity
3Stability of the object's composition
If multiple deposition and etching cycles are performed to form epitaxial source/drain features, then the features can be formed with adequate coverage, but the lateral dimension variations increase
Solution Approach 1:
The patent merges multiple deposition and etching cycles into a single unified deposition-etching cycle. The deposition process deposits semiconductor material with in-situ doping, and the etching process modifies the profile in one continuous sequence. This merging eliminates the lateral dimension variations that occur with multiple separate cycles while still achieving adequate coverage and stable epitaxial feature formation
Solution Approach 2:
The patent maintains continuity of useful action by performing deposition and etching in a single continuous cycle without interruption. The deposition of semiconductor material and the subsequent etching to modify the profile occur continuously, preventing the lateral dimension variations that arise from repeated cycling and ensuring consistent manufacturing precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise control over epitaxial source/drain feature profiles, reducing lateral variations and preventing electrical shorts, thereby enhancing the operational integrity of FinFET devices, especially at advanced technology nodes.
Implementation Method 1
performing a deposition process and an etching process only once to form a merged epitaxial source feature
Implementation Method 2
The etching process implements the chlorine-containing precursor, thereby modifying a profile of the merged epitaxial source feature
Implementation Method 3
performing a deposition process and an etching process only once to form a merged epitaxial source feature that spans the source regions
Data Source
AI summary
Source and drain formation techniques are disclosed herein for fin-like field effect transistors (FinFETs). An exemplary method for forming epitaxial source/drain features for a FinFET includes epitaxially growing a semiconductor material on a plurality of fins using a silicon-containing precursor and a chlorine-containing precursor. The semiconductor material merges to form an epitaxial feature spanning the plurality of fins, where the plurality of fins has a fin spacing that is less than about 25 nm. A ratio of a flow rate of the silicon-containing precursor to a flow rate of the chlorine-containing precursor is less than about 5. The method further includes etching back the semiconductor material using the chlorine-containing precursor, thereby modifying a profile of the epitaxial feature. The epitaxially growing and the etching back may be performed only once. In some implementations, where the FinFET is an n-type FinFET, the epitaxially growing also uses a phosphorous-containing precursor.