FinFET Source/Drain Extension Region Leakage Reduction

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Solution Overview

Problem

FinFETs with pure germanium or indium gallium arsenide channels experience higher leakage currents due to band-to-band tunneling, which hinders performance improvements despite increased carrier mobility.

Innovation Solution

The formation of a fin-shaped channel region with specific indium gallium arsenide compositions and the use of a barrier layer with reduced germanium concentration in the tunneling region between the channel and drain regions to decrease leakage currents, including epitaxial growth and mask pattern formation techniques.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If pure germanium or indium gallium arsenide channels are used to increase carrier mobility, then device speed and performance are improved, but leakage currents increase due to band-to-band tunneling

Engineering Contradiction:
Improvecarrier mobilityVSAvoidleakage current
Core Design Contradiction:
SpeedVSObject-generated harmful factors

Solution Approach 1:

The patent applies local quality by creating a barrier layer with specific compositional characteristics (reduced germanium concentration, indium gallium arsenide composition) localized in the tunneling region between channel and drain. This localized modification addresses the leakage problem specifically in the high-risk tunneling area without changing the overall high-mobility germanium channel properties, thus maintaining fast carrier transport while suppressing unwanted tunneling currents.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent employs composite materials by combining different semiconductor materials with distinct properties: a high-mobility germanium-based channel region (InxGa1-xAs with x≥0.5) and a barrier layer with reduced germanium content (InyGa1-yAs with y<0.5). This composite structure leverages the high carrier mobility of germanium while using the wider bandgap characteristics of the lower-germanium barrier layer to suppress band-to-band tunneling, achieving both speed and low leakage.

Inventive Principle:
Principle #40Composite materials

2Object-generated harmful factors

If a barrier layer with reduced germanium concentration is introduced to decrease leakage currents, then leakage is reduced, but device structure becomes more complex

Engineering Contradiction:
Improveleakage currentVSAvoidstructure complexity
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the drain region into distinct compositional zones: a barrier layer adjacent to the channel with reduced germanium concentration (y<0.5) and a bulk drain region with higher germanium content. This segmentation allows the barrier function to be localized to where it is most needed (at the channel-drain interface where tunneling occurs) while maintaining the beneficial high-mobility characteristics in the bulk drain, thus reducing leakage without requiring complete structural redesign.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces band-to-band tunneling currents, enhancing device performance by increasing the direct bandgap and minimizing leakage in the drain region, thereby improving overall device efficiency.

Implementation Method 1

those FinFETs may have higher leakage currents due to a band-to-band tunneling (BTBT) current in a drain region

Methodology Applied
Scientific EffectBand-to-band tunneling:

Implementation Method 2

forming a source/drain extension region between the channel region and the deep source/drain region. The source/drain extension region may include InyGa1−yAs

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS9583590B2Integrated circuit devices including FinFETs and methods of forming the same
Publication Date: 2017.02.28 SAMSUNG ELECTRONICS CO LTD
  • US9583590B2 patent drawing
  • US9583590B2 patent drawing
  • US9583590B2 patent drawing

AI summary

Methods of forming a finFET are provided. The methods may include forming a fin-shaped channel region including indium (In) on a substrate, forming a deep source/drain region adjacent to the channel region on the substrate and forming a source/drain extension region between the channel region and the deep source/drain region. Opposing sidewalls of the source/drain extension region may contact the channel region and the deep source/drain region, respectively, and the source/drain extension region may include InyGa1−yAs, and y is in a range of about 0.3 to about 0.5.