FinFET Source/Drain Height Reduction for Parasitic Resistance
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Solution Overview
Problem
FinFET devices face significant parasitic series resistance due to source/drain extension resistance, which is challenging to reduce without damaging the semiconductor structure or complicating the fabrication process, especially with limitations in implant energy and masking requirements.
Innovation Solution
The method involves reducing the height of the source/drain regions through etching, allowing for deeper implantation at lower energies and increasing the surface area for salicidation, while maintaining a suitable polysilicon gate height to compensate for spacer overetching and reduce parasitic series resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If ion implantation is performed at high energy to achieve deeper dopant penetration, then dopant concentration in source/drain regions is improved, but structural damage to the semiconductor structure increases
Solution Approach 1:
The source/drain region height is reduced through etching before ion implantation, creating a pre-condition that allows lower energy implantation to achieve the same dopant penetration depth. This preliminary structural modification enables subsequent doping without the need for high energy that would cause damage.
Solution Approach 2:
The physical dimensions of the source/drain regions are changed by reducing their height, which fundamentally alters the implantation geometry. This parameter change allows the implantation process to use lower energy while still achieving adequate dopant penetration, thereby avoiding structural damage.
2Ease of manufacture
If conventional planar CMOS technology is used, then fabrication process is simple, but parasitic features form in the channel beneath the gate creating current leakage
Solution Approach 1:
Instead of forming fins after gate formation as in conventional approaches, this invention forms the fins first and then forms the gate around them. This inverted sequence allows the gate to wrap around three sides of the fin structure, providing effective field control that prevents parasitic feature formation and current leakage while maintaining fabrication simplicity.
Solution Approach 2:
The gate structure transitions from a planar two-dimensional configuration to a three-dimensional configuration that wraps around the fin. This dimensional change allows the gate to control the channel from multiple directions (front, back, and sides), effectively suppressing parasitic current paths that occur in conventional planar devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables deeper dopant penetration and higher dopant concentration in source/drain regions, reducing parasitic series resistance and improving drive current, while minimizing structural damage and increasing the effectiveness of salicidation.
Implementation Method 1
reducing the height of the source/drain regions through etching
Implementation Method 2
Doping is typically accomplished using ion implantation from the front side of the wafer 22, and typically at an angle of about 30 degrees relative to a normal from the wafer 22
Data Source
AI summary
A method for making a transistor is provided which comprises (a) providing a semiconductor structure having a gate (211) overlying a semiconductor layer (203), and having at least one spacer structure (213) disposed adjacent to said gate; (b) removing a portion of the semiconductor structure adjacent to the spacer structure, thereby exposing a portion (215) of the semiconductor structure which underlies the spacer structure; and (c) subjecting the exposed portion of the semiconductor structure to an angled implant (253, 254).