FinFET Source/Drain Implantation for Deep Diffusion-Less Junctions
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Solution Overview
Problem
The challenge in semiconductor device manufacturing is to reduce channel resistance (Rch) and parasitic resistance (Rp) while minimizing the formation of P4V clusters and achieving precise dopant distribution in source/drain regions, particularly in FinFET devices, to enhance performance and integration density.
Innovation Solution
A high energy/low dose implantation process is employed to epitaxially grow semiconductor materials in the source/drain regions, followed by controlled doping to form deep diffusion-less pn junctions, reducing channel length, and modulating dopant profiles for improved device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional doping methods are used to reduce channel resistance, then channel resistance decreases, but parasitic resistance increases and P4V clusters form
Solution Approach 1:
The patent changes the implantation energy parameter to extremely high levels (5 MeV to 20 MeV) and adjusts the dose parameter to low levels (1×10^12 to 1×10^14 atoms/cm²). This parameter transformation allows dopant atoms to reach deep junction depths without forming P4V clusters, achieving low channel resistance without the harmful parasitic resistance that plagues conventional doping methods.
Solution Approach 2:
The patent performs preliminary high energy implantation to create deep dopant profiles before subsequent processing steps. This preliminary action establishes the deep junctions and dopant distribution in advance, preventing later formation of harmful P4V clusters and parasitic resistance during standard thermal processing and doping steps.
2Productivity
If minimum feature size is reduced to increase integration density, then integration density improves, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent replaces conventional low-energy ion implantation mechanics with high-energy ion implantation (5-20 MeV). This substitution fundamentally changes the dopant delivery mechanism, enabling precise deep junction formation at reduced feature sizes without the diffusion and clustering problems that limit manufacturing precision in conventional approaches.
Solution Approach 2:
The patent transitions from shallow, surface-near doping to deep, vertical junction formation by utilizing high implantation energies that penetrate hundreds of nanometers into the substrate. This dimensional shift in dopant placement enables precise control in the depth dimension while maintaining compatibility with reduced lateral feature sizes, thereby supporting higher integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces channel and parasitic resistances, minimizes P4V cluster formation, and enables precise junction definition, leading to enhanced semiconductor device performance and integration density.
Implementation Method 1
A first implantation process is performed on the semiconductor material. The first implantation process includes implanting first implants into the semiconductor material at a first energy. A second implantation process is performed on the semiconductor material. The second implantation process includes implanting second implants into the semiconductor material at a second energy different from the first energy.
Implementation Method 2
After performing the second implantation process, an anneal process is performed on the semiconductor material. The anneal process forms a doped region in the semiconductor fin at an interface between the semiconductor material and the semiconductor fin.
Data Source
AI summary
A semiconductor device and a method of forming the same are provided. The method includes forming a semiconductor fin extending from a substrate. A dummy gate stack is formed over the semiconductor fin. The dummy gate stack extends along sidewalls and a top surface of the semiconductor fin. The semiconductor fin is patterned to form a recess in the semiconductor fin. A semiconductor material is deposited in the recess. An implantation process is performed on the semiconductor material. The implantation process includes implanting first implants into the semiconductor material and implanting second implants into the semiconductor material. The first implants have a first implantation energy. The second implants have a second implantation energy different from the first implantation energy.