FinFET Epitaxial Source/Drain Layout for Isolation and Contact Alignment

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Solution Overview

Problem

As IC feature sizes shrink, multigate devices face challenges with epitaxial source/drain configurations that lead to unintentional merging, electrical shorting, and performance degradation due to reduced contact landing windows and alignment issues, particularly in FinFETs.

Innovation Solution

Optimized lateral dimensions and spacings for epitaxial source/drains in FinFETs, including increased widths and tailored spacings to minimize merging and enhance contact landing windows, while accounting for different type FinFET profiles and additional isolation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If IC feature sizes are reduced to increase device density, then more devices can be packed in a smaller area, but epitaxial source/drain structures experience unintentional merging and electrical shorting

Engineering Contradiction:
Improvedevice densityVSAvoidsource/drain isolation
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The source/drain region is segmented into multiple discrete epitaxial source/drain structures separated by isolation fins rather than forming continuous merged structures. This segmentation prevents unwanted electrical connections while maintaining the benefits of scaled feature sizes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Isolation fins are introduced as intermediary structures between adjacent epitaxial source/drain regions. These isolation fins act as barriers that prevent merging and electrical shorting of source/drain structures while allowing the overall device density to be increased through scaling.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If epitaxial source/drain widths are increased to improve contact landing windows, then contact alignment becomes easier, but the spacing between source/drain structures must be increased to prevent merging

Engineering Contradiction:
Improvecontact alignmentVSAvoidsource/drain spacing
Core Design Contradiction:
Manufacturing precisionVSLength of stationary object

Solution Approach 1:

The solution applies different dimensional characteristics to different parts of the source/drain structure. The epitaxial source/drain structures have optimized widths for contact alignment in their local regions, while the isolation fins provide spacing in the horizontal direction. This local optimization allows improved contact alignment without requiring increased overall spacing between devices.

Inventive Principle:
Principle #3Local quality

3Productivity

If multigate devices are scaled down to achieve smaller IC feature sizes, then higher integration is achieved, but manufacturing complexity increases due to alignment issues

Engineering Contradiction:
Improveintegration levelVSAvoidmanufacturing process complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The isolation fins are formed before the epitaxial source/drain structures are deposited. This preliminary action establishes the spacing and isolation framework in advance, which then guides the subsequent source/drain formation process and simplifies alignment operations rather than increasing manufacturing complexity.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enhances FinFET density and performance by preventing unintentional merging, improving contact alignment, and reducing device remain defects, thus maintaining reliability and functionality in advanced technology nodes.

Implementation Method 1

epitaxial source/drain configurations

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS12550363B2Epitaxial source/drain configurations for multigate devices
Publication Date: 2026.02.10 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12550363B2 patent drawing
  • US12550363B2 patent drawing
  • US12550363B2 patent drawing

AI summary

A semiconductor structure includes a first multigate device, a second multigate device, and an isolation structure. The first multigate device has a first channel layer extending between first epitaxial source/drains along a first direction. The second multigate device has a second channel layer extending between second epitaxial source/drains along the first direction. The first epitaxial source/drains and second epitaxial source/drains have a first width and a second width, respectively, along a second direction that is different than the first direction. The isolation structure includes a dielectric fin over a substrate isolation feature. The dielectric fin is between the first epitaxial source/drains and the second epitaxial source/drains. The dielectric fin has a third width along the second direction. A distance between the first epitaxial source/drains and the second epitaxial source/drains along the second direction is greater than the third width, less than the second width, and less than the first width.