FinFET Source/Drain Merged Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, the complexity of their fabrication increases, making it challenging to form reliable devices at smaller scales.
Innovation Solution
The formation of semiconductor device structures using FinFETs, where fins are patterned using photolithography and self-aligned processes, and nanostructure transistors are patterned using double-patterning or multi-patterning processes, allowing for smaller pitches and more complex designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but fabrication process complexity increases and manufacturing difficulty increases
Solution Approach 1:
The fabrication process is divided into multiple discrete stages including forming mandrels, depositing first spacers, removing mandrels, depositing second spacers, and selective etching. Each stage accomplishes a specific portion of the overall pattern formation, making the complex process more manageable and controllable while achieving high functional density
Solution Approach 2:
Mandrels are formed in advance as sacrificial structures that define the eventual source/drain regions. These preliminary structures guide subsequent spacer deposition and material formation, ensuring precise positioning before the actual active materials are deposited
2Productivity
If feature sizes continue to decrease to increase functional density, then chip area utilization improves, but fabrication reliability decreases
Solution Approach 1:
The spacer structures self-align to the mandrels and gate electrodes through conformal deposition, automatically defining precise source/drain regions without requiring additional alignment steps. This self-aligned approach eliminates alignment errors and improves fabrication reliability at small feature sizes
Solution Approach 2:
The process uses different deposition methods (CVD, PECVD, ALD) and materials (silicon oxide, silicon nitride, silicon germanium) with varying properties to control spacer thickness, composition, and stress characteristics, enabling precise control over source/drain region formation and improving device reliability
3Ease of manufacture
If conventional planar transistors are used, then fabrication is simpler, but parasitic capacitance is higher and performance is lower
Solution Approach 1:
The transistor structure transitions from a planar two-dimensional layout to a three-dimensional FinFET configuration with vertical fins extending from the substrate. This dimensional change increases the effective channel area and gate control while reducing parasitic capacitance, improving performance without significantly complicating the fabrication process
4Device complexity
If source/drain regions are formed without merged portions, then fabrication is simpler, but parasitic capacitance between adjacent source/drain structures is higher
Solution Approach 1:
Adjacent source/drain structures are merged through selective removal of spacer material between them, creating continuous semiconductor regions that eliminate the capacitive coupling that would exist between separate structures. This merging reduces parasitic capacitance while the selective nature of the process keeps fabrication complexity manageable
Data Source
AI summary
A method for forming a semiconductor device structure is provided. The method includes providing a substrate having a base, a first fin, and a second fin over the base. The method includes forming a gate stack over the first fin and the second fin. The method includes forming a first spacer over gate sidewalls of the gate stack and a second spacer adjacent to the second fin. The method includes partially removing the first fin and the second fin. The method includes forming a first source/drain structure and a second source/drain structure in the first trench and the second trench respectively. A first ratio of a first height of the first merged portion to a second height of a first top surface of the first source/drain structure is greater than or equal to about 0.5.