FinFET Source/Drain Modulation for Uniform Recess Depths
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Solution Overview
Problem
Advanced integrated circuits face issues such as short channel effects, junction leakage, and resistance variations due to dimensional variations in source/drain features, leading to challenges in circuit design, performance, and fabrication uniformity.
Innovation Solution
A method involving ion implantation to modify the etch rate of source/drain regions during the etching process, optimizing the recess depth and structure of field-effect transistors (FETs) in different circuit areas to enhance performance and uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If source/drain features are shrunk to enable advanced technology nodes, then device scaling is achieved, but dimensional variation causes short channel issues, junction leakage and resistance variations
Solution Approach 1:
The patent applies ion implantation to source/drain regions before the etching process to pre-modify the etch rate. This preliminary action compensates for dimensional variations that would otherwise occur during etching, ensuring more uniform source/drain recess depths across different circuit areas even as features are scaled down to advanced nodes
Solution Approach 2:
The patent introduces doping species selectively into specific source/drain regions to create localized etch rate modifications. This allows different circuit areas to have tailored etch characteristics, compensating for dimensional variations in a location-specific manner while maintaining overall scaling benefits
2Reliability
If source/drain regions are recessed to optimize device performance, then transistor performance is improved, but non-uniform recess depths cause variations in source/drain resistance and parasitic capacitance
Solution Approach 1:
Ion implantation is performed before etching to pre-establish the desired etch rate distribution. This preliminary modification ensures that subsequent etching produces uniform recess depths across all source/drain regions, eliminating variations in source/drain resistance and parasitic capacitance while maintaining optimized transistor performance
Solution Approach 2:
The patent uses the etch rate modification as a feedback mechanism to compensate for dimensional variations. By pre-modifying the etch rate based on expected dimensional variations, the process self-corrects to produce uniform recess depths, ensuring consistent transistor characteristics across the chip
3Adaptability or versatility
If different circuit areas have different gate spacings, then circuit design flexibility is improved, but etch loading effect causes non-uniform etch rates across circuit areas
Solution Approach 1:
The patent applies ion implantation selectively to source/drain regions in different circuit areas to create location-specific etch rate modifications. This local quality approach compensates for the etch loading effect caused by different gate spacings, ensuring uniform etch rates across diverse circuit areas while maintaining design flexibility
Solution Approach 2:
The patent preemptively counteracts the etch loading effect by modifying the etch rate through ion implantation before the etching process. This preliminary anti-action neutralizes the non-uniform etch rates that would otherwise result from different gate spacings, allowing diverse circuit designs to be fabricated with uniform precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves circuit performance, power efficiency, and packing density while reducing fabrication costs by achieving uniform source/drain recess depths and structures across various circuit areas.
Implementation Method 1
performing an ion implantation to introduce a doping species to a first active region
Data Source
AI summary
The present disclosure provides a fabrication method that includes providing a workpiece having a semiconductor substrate with a first circuit area and a second circuit area; forming a first active region within the first circuit area and a second active region within the second circuit area; forming a first gate structure on the first active region and a second gate structure on the second active region; introducing a doping species to the first active region but not the second active region; performing an etching process, thereby simultaneously recessing both first source/drain regions of the first active region and second source/drain regions of the second active region at a same etch rate; and thereafter, epitaxially growing first source/drain features within the first source/drain regions and second source/drain features within the second source/drain regions.