FinFET Source/Drain Multi-Layer Structure for Lower Leakage
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating reliable three-dimensional fin field effect transistors (FinFETs) due to the increasing complexity and difficulty of processing as feature sizes decrease, particularly in forming a reliable semiconductor structure with reduced leakage and improved current flow.
Innovation Solution
A method involving a gate-replacement process is employed, where a fin structure is formed on a substrate with isolation regions, dummy gate structures and hard mask layers are deposited, followed by the growth of source/drain epitaxial layers with different dopants to reduce drain-induced barrier lowering (DIBL) and improve on-resistance, and dielectric and blocking layers are used to control the formation of the FinFET structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature sizes are decreased to increase functional density, then the number of interconnected devices per chip area increases, but fabrication complexity and difficulty increase
Solution Approach 1:
The source/drain structure is divided into multiple epitaxial layers with different dopant compositions. The first source/drain epitaxial layer has a first dopant concentration and the second source/drain epitaxial layer has a second dopant concentration, creating a segmented structure that addresses fabrication challenges at reduced feature sizes
Solution Approach 2:
Different regions of the source/drain structure are assigned different dopant concentrations to optimize local electrical properties. The first epitaxial layer provides one dopant concentration while the second epitaxial layer provides a different dopant concentration, allowing tailored electrical characteristics in different regions
2Ease of manufacture
If dopant diffusion is allowed to occur naturally, then manufacturing process is simpler, but drain-induced barrier lowering increases and on-resistance worsens
Solution Approach 1:
The patent applies preliminary anti-action by using epitaxial growth to pre-form source/drain structures with controlled dopant concentrations before metal deposition. The first and second source/drain epitaxial layers are grown with specific dopants that counteract unwanted dopant diffusion during subsequent processing steps
Solution Approach 2:
The source/drain epitaxial layers are formed in advance before the metal layer is deposited. This preliminary action establishes the electrical characteristics of the source/drain regions before subsequent processing, preventing later modifications that could degrade performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of FinFETs with reduced leakage and improved current flow by suppressing dopant diffusion into the channel region, thereby enhancing the reliability and performance of the semiconductor structure.
Implementation Method 1
growth of source/drain epitaxial layers with different dopants to reduce drain-induced barrier lowering (DIBL)
Implementation Method 2
suppressing dopant diffusion into the channel region, thereby enhancing the reliability and performance of the semiconductor structure
Data Source
AI summary
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate structure. The semiconductor structure also includes a S/D silicide layer formed on the S/D epitaxial layer, and the S/D silicide layer has a first width, the S/D epitaxial layer has a second width, and the first width is smaller than the second width. The semiconductor structure includes a dielectric spacer between the gate structure and the S/D silicide layer, and a top surface of the dielectric spacer is lower than a top surface of the gate structure.