FinFET Source/Drain Recess Etching for Epitaxial Proximity

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Solution Overview

Problem

In the semiconductor industry, the development of three-dimensional designs such as fin field effect transistors (FinFETs) with metal gate structures faces challenges in achieving optimal source/drain epitaxial growth due to limitations in recess etching techniques, which affect device performance and efficiency.

Innovation Solution

A method involving multiple etching steps (isotropic and anisotropic) is employed to form source/drain recesses in fin structures, followed by epitaxial growth, allowing for precise control of epitaxial layer formation and proximity to the channel region, improving transistor performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional recess etching techniques are used, then the manufacturing process is simple, but the proximity between source/drain epitaxial layers and channel region cannot be optimized

Engineering Contradiction:
Improveproximity control between epitaxial layers and channel regionVSAvoidetching process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The etching process is divided into multiple sequential steps: first recess etching to form initial source/drain regions, followed by second recess etching to further define the regions closer to the channel, and third recess etching to achieve final precise positioning. This segmentation allows progressive refinement of the epitaxial layer proximity without requiring a single complex etching step.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary recess etching steps before epitaxial growth to pre-form the source/drain regions at desired positions and depths. This preliminary action ensures that when epitaxial layers are subsequently grown, they form precisely at the intended proximity to the channel region, achieving optimal device performance before final processing steps.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If epitaxial layers are placed closer to the channel region, then transistor performance is improved, but control of epitaxial growth becomes more difficult

Engineering Contradiction:
Improvetransistor performanceVSAvoidepitaxial growth control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent performs preliminary recess etching steps before epitaxial growth to pre-form the source/drain regions at desired positions and depths. This preliminary action ensures that when epitaxial layers are subsequently grown, they form precisely at the intended proximity to the channel region, achieving optimal device performance before final processing steps.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent employs multiple etching steps with different parameters (isotropic and anisotropic etching with varying selectivity and depth control) to precisely define the source/drain region geometry before epitaxial growth. By carefully controlling etching depth, width, and profile in each step, the patent creates optimal conditions for subsequent epitaxial layer formation at controlled proximity to the channel.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the proximity between source/drain epitaxial layers and the channel region, leading to improved transistor performance and efficiency by allowing for closer epitaxial layer placement to the gate electrode.

Implementation Method 1

sources and drains are formed by using an epitaxial growth method

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS11121217B2Semiconductor device and manufacturing method thereof
Publication Date: 2021.09.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11121217B2 patent drawing
  • US11121217B2 patent drawing
  • US11121217B2 patent drawing

AI summary

In a method of manufacturing a semiconductor device, a fin structure is formed over a substrate. The fin structure has a channel region and a source/drain region. A gate structure is formed over the channel region of the fin structure. A first source/drain etching is performed to recess the source/drain region of the fin structure. After the first source/drain etching, a second source/drain etching is performed to further recess the source/drain region of the fin structure. After the second source/drain etching, a third source/drain etching is performed to further recess the source/drain region of the fin structure, thereby forming a source/drain recess. One or more epitaxial layers are formed in the source/drain recess. The first source/drain etching is isotropic etching and the second source/drain etching is anisotropic etching.