FinFET Source/Drain Structure for Lower Contact Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As integrated circuits shrink, the contact resistance between metal contact plugs and semiconductor regions in FinFETs increases due to smaller silicide regions, leading to higher electrical contact resistance, which is a severe problem in Fin Field-Effect Transistors.
Innovation Solution
The process involves forming semiconductor fins with recessed source/drain regions, followed by epitaxial growth and silicidation, which increases the contact area between the contact plugs and the source/drain regions, reducing contact resistance by exposing sidewalls of the source/drain regions and forming silicide regions on these surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integrated circuits are downsized, then circuit density and integration are improved, but contact resistance between metal contact plugs and semiconductor regions increases
Solution Approach 1:
The patent transitions from planar contact geometry to three-dimensional contact structures. Specifically, it forms contact regions that extend along the sidewalls of the fin structure, utilizing the vertical dimension to increase contact area. The contact structure includes a first portion contacting the top surface and a second portion extending along the sidewall, effectively adding a dimensional aspect to the contact interface.
Solution Approach 2:
The contact structure is nested within the overall FinFET structure, with the contact region integrated into the fin geometry. The contact structure includes portions that are embedded within or adjacent to the fin sidewalls, creating a nested configuration where the contact follows the three-dimensional shape of the fin structure.
2Manufacturing precision
If silicide regions are made smaller to match downsized transistors, then transistor scaling is achieved, but contact area between contact plugs and silicide regions decreases
Solution Approach 1:
The patent compensates for reduced planar contact area by extending the contact structure into the vertical dimension. The contact region includes a second portion that extends along the sidewall of the fin structure, utilizing the vertical space to increase total contact area without increasing the lateral footprint of the device.
Solution Approach 2:
The contact structure is designed to maximize surface area through geometric complexity rather than material porosity. The contact region follows the three-dimensional geometry of the fin sidewalls, creating a high surface-area-to-footprint ratio contact interface that increases contact area without requiring porous materials.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the source/drain contact resistance by increasing the contact area, thereby improving the electrical performance of FinFETs as integrated circuits scale down.
Implementation Method 1
A typical silicidation process includes forming a metal layer on the surfaces of the semiconductor regions, and then performing an annealing, so that the metal layer reacts with the semiconductor regions to form the silicide regions.
Implementation Method 2
The process involves forming semiconductor fins with recessed source/drain regions, followed by epitaxial growth and silicidation
Data Source
AI summary
An integrated circuit structure includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, with the insulation regions including first top surfaces and second top surfaces lower than the first top surfaces, a semiconductor fin over the first top surfaces of the insulation regions, a gate stack on a top surface and sidewalls of the semiconductor fin, and a source/drain region on a side of the gate stack. The source/drain region includes a first portion having opposite sidewalls that are substantially parallel to each other, with the first portion being lower than the first top surfaces and higher than the second top surfaces of the insulation regions, and a second portion over the first portion, with the second portion being wider than the first portion.