FinFET Source-Drain Extension Formation With In-Situ SEG Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The formation of horizontal source/drain extensions in finFETs is challenging due to issues such as amorphization of the fin-shaped channel region, intermixing between silicon and silicon-germanium layers, and difficulty in precise dopant placement, which are exacerbated by conventional ion implantation techniques and increased thermal budgets.
Innovation Solution
An anisotropic and isotropic etch process is used to create cavities in the finFET structure, followed by selective epitaxial growth (SEG) to form doped extension regions without pre-clean processes, allowing precise dopant placement and minimizing thermal exposure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional ion implantation techniques are used to form source/drain extensions in finFETs, then dopant can be deposited to the source/drain region, but the fin-shaped channel region becomes amorphized or damaged and intermixing occurs between silicon channel and silicon-germanium sacrificial layer
Solution Approach 1:
The patent performs preliminary actions by forming cavities in the source/drain extension regions before epitaxial growth, and by removing sidewall spacers to expose the cavity surfaces. This preliminary preparation enables subsequent selective epitaxial growth to occur precisely in the desired locations without damaging the channel region, thereby achieving both precise dopant placement and channel integrity.
Solution Approach 2:
The patent replaces the mechanical ion implantation process with a chemical epitaxial growth process. Instead of using ion implantation to deposit dopants (which causes amorphization and intermixing), the invention uses selective epitaxial growth to form doped semiconductor material in the cavities. This substitution eliminates the harmful mechanical effects while achieving the desired dopant placement precision.
2Reliability
If thermal anneal is performed to repair ion implantation damage, then the channel region damage can be repaired, but the thermal budget of the finFET device increases
Solution Approach 1:
The patent converts the potential harm of cavity formation (which could be seen as creating defects) into a benefit by using the cavities as precise templates for epitaxial growth. The cavities, formed by controlled etching, become the exact locations where doped material needs to be deposited, eliminating the need for thermal annealing to repair damage while maintaining channel region integrity.
3Reliability
If sidewall spacers are kept in place during doping, then the finFET structure is protected, but precise dopant placement in the source/drain extension region becomes difficult
Solution Approach 1:
The patent applies segmentation by dividing the source/drain region into distinct components: cavities formed in the semiconductor material, and sidewall spacers formed on the sidewalls. This segmentation allows the spacers to serve as protective masks during cavity formation, while the cavities themselves become the precise locations for subsequent epitaxial growth, achieving both structure protection and precise dopant placement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables precise formation of doped extension regions inaccessible by conventional ion implantation, reducing defects and thermal budgets, and introduces tensile strain for improved charge mobility in the finFET channel region.
Implementation Method 1
An anisotropic etch process is performed on a semiconductor material on a semiconductor substrate to expose a surface in the semiconductor material
Implementation Method 2
An isotropic etch process is performed on an exposed sidewall to recess the semiconductor material that is disposed between the existing structure and the bulk semiconductor portion of the semiconductor substrate by a distance to form a cavity
Implementation Method 3
A layer of deposited material is formed via a selective epitaxial growth (SEG) process on a surface of the cavity
Data Source
AI summary
A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.