FinFET Source/Drain Epitaxy Segmentation for Electrical Isolation
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Solution Overview
Problem
In FinFET semiconductor manufacturing, epitaxial growth of source and drain regions leads to current crowding and electrical shorts due to uneven growth profiles and reduced spacing between neighboring fins, making it difficult to achieve optimal stress engineering and low resistance while avoiding shorts.
Innovation Solution
The method involves forming disposable spacers on silicon fin structures, anisotropically etching to create voids, and epitaxially growing silicon in these voids to form un-merged source/drain regions, while maintaining merged regions on un-etched fins, optimizing both stress engineering and spacing to prevent electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If selective epitaxial growth is performed on source/drain areas to increase silicon volume for stress engineering and lower resistance, then device performance is improved, but the epitaxial layers extend laterally and merge between neighboring fins, reducing spacing and causing electrical shorts
Solution Approach 1:
The source/drain regions are segmented into merged regions (for stress engineering and low resistance) and un-merged regions (for electrical isolation). This is achieved by selectively removing disposable spacers from certain fins before epitaxial growth, allowing those fins to have merged source/drain regions, while other fins retain spacers that prevent merging. The segmentation resolves the contradiction by allowing both merged and un-merged regions to coexist on the same semiconductor structure.
Solution Approach 2:
Different fins are given different local qualities regarding source/drain merging. Some fins are designed with merged source/drain regions while adjacent fins have un-merged regions. This local differentiation is controlled by the selective presence or removal of disposable spacers, allowing optimization of device performance in specific locations while preventing electrical shorts in other locations.
2Volume of stationary object
If epitaxial growth is performed to form source/drain regions, then silicon volume is increased for better stress engineering, but the growth profile becomes uneven with facets forming, reducing manufacturing precision
Solution Approach 1:
Disposable spacers are formed on the fins before the epitaxial growth process. These spacers serve as preliminary structures that define the maximum lateral extent of the epitaxial source/drain regions. During epitaxial growth, the spacers prevent lateral overgrowth and facet formation, ensuring that the source/drain regions grow uniformly vertically without developing uneven profiles or facets.
Solution Approach 2:
The disposable spacers act as intermediary structures between the fin structures and the epitaxial source/drain regions. They mediate the epitaxial growth process by providing a physical barrier that controls lateral growth, thereby ensuring uniform vertical growth profiles while still allowing the necessary silicon volume to be accumulated for stress engineering.
3Productivity
If fin structures are made narrow to achieve small scale processes, then device scaling is improved, but current crowding occurs and contact plug placement becomes difficult
Solution Approach 1:
Disposable spacers are formed on the narrow fins before subsequent processing steps. These spacers extend the effective width of the fin structures at critical locations, providing adequate spacing for contact plug placement and relieving current crowding effects. The spacers are formed in advance to prepare the structure for subsequent manufacturing steps, enabling both small-scale device dimensions and adequate operational margins.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of both merged and un-merged source/drain regions at a given fin-pitch, optimizing device performance by maintaining silicon volume and spacing, thereby enhancing stress engineering, reducing resistance, and preventing electrical shorts.
Implementation Method 1
Selective epitaxial growth (SEG) technology may be employed. In the prior art, SEG technology has been widely used at 32 nm node and beyond in planar CMOS technology. The SEG is performed on source/drain areas using, for example, SiGe for p-type transistors and Si:C for n-type transistors.
Implementation Method 2
The precursor gasses can also be mixed with some percentage of germanium for SiGe growth, or dopants (e.g., C, B, P, and/or As) for in-situ doping.
Data Source
AI summary
Methods of manufacturing semiconductor integrated circuits having FinFET structures with epitaxially formed source and drain regions are disclosed. A method of fabricating an integrated circuit includes forming a plurality of silicon fin structures on a semiconductor substrate, epitaxially growing a silicon material on the fin structures, wherein a merged source/drain region is formed on the fin structures, and anisotropically etching at least one of the merged source drain regions to form an un-merged source/drain region.