FinFET Source/Drain Epitaxy With Silane for Higher Phosphorus Doping
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Solution Overview
Problem
The challenge in FinFET manufacturing lies in achieving high phosphorous atomic percentages in source/drain regions to reduce resistance, as conventional methods struggle to increase dopant concentration beyond certain limits without compromising process efficiency and stability.
Innovation Solution
Incorporating silane into the process gases during epitaxial growth of source/drain regions, specifically using a combination of dichlorosilane and phosphine with varying silane flow rates, allows for increased phosphorous atomic percentages up to 11% without the need for excessive phosphine flow, which helps in forming stable Si—P bonds and enhancing dopant concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional epitaxial growth methods are used with standard process gases, then process stability is maintained, but phosphorous atomic percentage in source/drain regions is limited and resistance remains high
Solution Approach 1:
The patent changes the chemical composition parameters of the process gas by introducing silane (SiH4) alongside dichlorosilane (SiH2Cl2) and phosphine (PH3). This parameter change enables the formation of stable Si-P bonds during epitaxial growth, allowing phosphorous atomic percentage to increase from conventional limits to over 11% while maintaining process stability. The specific parameter adjustment includes optimizing silane flow rate between 5-50 sccm to achieve the desired dopant concentration.
2Quantity of substance
If phosphine flow rate is increased to achieve higher phosphorous concentration, then dopant concentration increases, but process stability deteriorates and excessive phosphine causes adverse effects
Solution Approach 1:
The patent introduces silane as an intermediary substance that mediates between phosphine and the silicon substrate during epitaxial growth. Silane reacts with phosphine to form volatile phosphorosilane species that incorporate phosphorous into the silicon lattice more efficiently. This intermediary mechanism allows achieving high dopant concentration (phosphorous atomic percentage >11%) with reduced phosphine flow rates, thereby maintaining process stability and avoiding the harmful effects of excessive phosphine.
3Reliability
If dopant concentration is increased to reduce resistance, then electrical conductivity improves, but manufacturing complexity increases
Solution Approach 1:
The patent merges multiple functions into a single epitaxial growth process by simultaneously achieving dopant incorporation, resistance reduction, and source/drain region formation. The combined process gas mixture of dichlorosilane, phosphine, and silane enables all these functions to be accomplished in one step rather than requiring separate doping and growth processes. This merging approach improves electrical conductivity through high phosphorous concentration while avoiding the need for additional manufacturing steps, thus reducing overall manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases phosphorous atomic percentages in FinFET source/drain regions, reducing resistance and improving transistor performance by allowing for higher dopant concentrations while maintaining process stability and efficiency.
Implementation Method 1
forming stable Si—P bonds and enhancing dopant concentration
Implementation Method 2
performing a first epitaxy to grow a first epitaxy layer extending into the recess... performing a second epitaxy to grow a second epitaxy layer extending into the recess and over the first epitaxy layer
Implementation Method 3
using a combination of dichlorosilane and phosphine with varying silane flow rates, allows for increased phosphorous atomic percentages up to 11%
Data Source
AI summary
A method includes recessing a semiconductor fin to form a recess, wherein the semiconductor fin protrudes higher than isolation regions on opposite sides of the semiconductor fin, and performing a first epitaxy to grow a first epitaxy layer extending into the recess. The first epitaxy is performed using a first process gas comprising a silicon-containing gas, silane, and a phosphorous-containing gas. The first epitaxy layer has a first phosphorous atomic percentage. The method further includes performing a second epitaxy to grow a second epitaxy layer extending into the recess and over the first epitaxy layer. The second epitaxy is performed using a second process gas comprising the silicon-containing gas, silane, and the phosphorous-containing gas. The second epitaxy layer has a second phosphorous atomic percentage higher than the first phosphorous atomic percentage.