FinFET Epitaxial Source/Drain Layout for Void-Controlled Scaling

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Solution Overview

Problem

The semiconductor industry faces challenges in fabricating high-density, high-performance semiconductor devices due to issues related to the epitaxial source/drain structure, particularly in forming voids and managing the manufacturing process effectively.

Innovation Solution

The proposed solution involves a method for manufacturing a semiconductor device with an epitaxial source/drain structure, where a sidewall spacer layer with specific dielectric materials is formed, and the source/drain regions are recessed and epitaxially grown, allowing for the formation of voids and improved device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If epitaxial growth method is used to form source/drain regions, then device density and performance are improved, but void formation occurs in the epitaxial source/drain structure

Engineering Contradiction:
Improvedevice densityVSAvoidvoid formation
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The epitaxial source/drain structure is divided into multiple segments: a first epitaxial source/drain region with higher doping concentration and a second epitaxial source/drain region with lower doping concentration. This segmentation allows each region to serve different functional purposes, with the first region providing carrier supply and the second region reducing void formation, thereby resolving the contradiction between device density and void formation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different doping concentrations are applied to different spatial locations within the source/drain structure. The first epitaxial source/drain region uses a first doping concentration optimized for carrier generation, while the second epitaxial source/drain region uses a second doping concentration optimized for void suppression. This local quality differentiation enables simultaneous achievement of high device density and reduced void formation.

Inventive Principle:
Principle #3Local quality

2Reliability

If higher doping concentration is used in epitaxial source/drain region, then device performance is improved, but void formation is exacerbated

Engineering Contradiction:
Improvedevice performanceVSAvoidvoid formation
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The source/drain structure is segmented into two regions with different doping concentrations. The first epitaxial source/drain region employs higher doping concentration to ensure device performance and carrier supply, while the second epitaxial source/drain region employs lower doping concentration to minimize void formation. This segmentation strategy resolves the contradiction between device performance and void formation by distributing different doping levels to appropriate spatial locations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The doping concentration is optimized locally for different regions: higher doping in the first epitaxial source/drain region for performance critical areas, and lower doping in the second epitaxial source/drain region for void-sensitive areas. This local quality approach enables simultaneous achievement of high reliability and manufacturing precision.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the formation of semiconductor devices with enhanced performance and density by effectively managing the epitaxial source/drain structure and void formation, thereby addressing the challenges faced in current manufacturing processes.

Implementation Method 1

sources and drains are formed by using an epitaxial growth method

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS12283624B2Method of manufacturing a semiconductor device and a semiconductor device
Publication Date: 2025.04.22 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12283624B2 patent drawing
  • US12283624B2 patent drawing
  • US12283624B2 patent drawing

AI summary

In a method of manufacturing a semiconductor device, a first fin structure, a second fin structure, a first wall fin structure and a second wall fin structure are formed over a substrate. The first and second fin structures are disposed between the first and second wall fin structures, and lower portions of the first and second fin structures and the first and second wall fin structures are embedded in the isolation insulating layer and upper portions thereof are exposed from the isolation insulating layer. A sidewall spacer layer is formed on sidewalls of the first and second fin structures. Source/drain regions of the first and second fin structures are recessed. An epitaxial source/drain structure is formed over the recessed first and second fin structures. A width W1 of the first and second fin structures is smaller than a thickness W2 of the sidewall spacer layer.