FinFET Source-Sharing Layout for Narrow Pitch and Matching
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Solution Overview
Problem
Existing semiconductor devices with fin field effect transistors (FinFETs) face challenges in achieving a narrow pitch width and excellent matching between transistors due to the shadow effect of ion injection and process impacts, leading to poor current flow alignment and increased pitch width.
Innovation Solution
The semiconductor device is designed with first and second transistors connected in parallel, sharing a source and having fin activation layers arranged adjacent to each other, with gate electrodes formed via an insulating film between drain and source layers, and dummy layers to maintain structure, allowing for opposite current flow directions between transistors to cancel each other out and reduce process impacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If transistors are arranged with conventional source sharing configuration, then manufacturing process is simplified, but pitch width increases and matching between transistors deteriorates due to shadow effect of ion injection
Solution Approach 1:
The patent inverts the conventional current flow direction arrangement between adjacent transistors. Instead of having currents flow in the same direction, the invention configures adjacent transistors to have opposite current flow directions, which eliminates the shadow effect of ion injection and improves transistor matching precision while maintaining reasonable pitch width
2Productivity
If pitch width between transistors is reduced, then device integration density improves, but process impacts and shadow effect of ion injection increase leading to poor transistor matching
Solution Approach 1:
The patent converts the harmful shadow effect of ion injection into a beneficial configuration by deliberately arranging current flows in opposite directions. This configuration causes the shadow effects to cancel each other out, allowing narrow pitch width to be achieved without sacrificing transistor matching precision
3Ease of operation
If conventional transistor configuration is used, then current flow alignment is simpler, but pitch width increases and device area expands
Solution Approach 1:
The patent inverts the conventional approach by configuring adjacent transistors with opposite current flow directions. This not only reduces pitch width and device area but also maintains current flow alignment through systematic opposite-direction configuration of source and drain connections
Data Source
Figure 1
Figure 2A~2B
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AI summary
Disclosed herein is a semiconductor device including: first and second transistors, each of the first and second transistors being formed with a plurality of fin transistors, and the first and second transistors being connected in parallel to electrically share a source, wherein the plurality of fin transistors each include a fin activation layer, the fin activation layer protruding from a semiconductor substrate, a source layer serving as the source being formed on one end, and a drain layer on the other end of the fin activation layer so as to form a channel region, the fin activation layers are arranged adjacent to each other in parallel, and the drain layers are disposed so that the currents flow through the plurality of fin transistors in opposite directions between the first and second transistors.