FinFET Active Pattern Spacer Design for Parasitic Capacitance Reduction
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Solution Overview
Problem
As semiconductor devices become highly integrated, they face challenges in achieving high performance due to the scaling down of transistors, which affects their operating characteristics and reliability.
Innovation Solution
The method involves forming a semiconductor device with a substrate having an active pattern and a gate electrode, where a first spacer with a stepped shape is created, with a thicker lower portion and a thinner upper portion, to facilitate the formation of a channel pattern and reduce parasitic capacitance, thereby enhancing electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are scaled down to achieve high integration, then device density increases, but operating characteristics and reliability deteriorate
Solution Approach 1:
The patent transitions from planar transistors to three-dimensional FinFET structures by creating vertically extending fin-shaped active regions. This dimensional change increases the effective channel area and surface area for charge carrier transport without increasing the footprint area, thereby improving device performance and reliability while maintaining high integration density.
Solution Approach 2:
The gate electrode is divided into multiple segments positioned at different heights along the fin structure, with each gate segment controlling a specific portion of the channel. This segmentation allows for optimized electrical characteristics and improved reliability by independently tuning gate control over different channel regions while maintaining compact integration.
2Ease of manufacture
If conventional spacer structures are used with uniform thickness, then manufacturing is simpler, but etching precision and electrical characteristics are insufficient
Solution Approach 1:
The spacer structure is segmented into multiple portions with different thicknesses along the vertical direction. The first spacer portion has a first thickness and the second spacer portion has a second thickness different from the first. This segmentation enables precise control of etching depth and active pattern dimensions while maintaining a relatively simple manufacturing process using sequential deposition and etching steps.
Solution Approach 2:
Different portions of the spacer are given different thicknesses to serve different functions: the first spacer portion provides structural support and defines the upper boundary, while the second spacer portion enables precise etching control at a different depth level. This local differentiation of spacer quality optimizes both manufacturing precision and electrical characteristics.
Data Source
AI summary
Semiconductor devices and methods of fabricating the same are provided. The method includes forming on a substrate an active pattern that protrudes from the substrate and extends in one direction; forming on the active pattern a sacrificial gate structure that extends in a direction intersecting the active pattern; forming on a side surface of the sacrificial gate structure a first spacer including a first portion at a lower level than a top surface of the active pattern and a second portion on the first portion, and reducing a thickness of the second portion of the first spacer.