FinFET Gate Spacer Structure for Contact Space and Lower Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in the semiconductor industry is the difficulty in forming and aligning minute features in integrated circuits, particularly in FinFET gate structures, which affects yield, performance, and variability due to the complexity of scaling down device sizes.
Innovation Solution
The solution involves thinning dielectric gate spacers alongside FinFET gates to create more space for contacts, allowing easier fabrication and alignment, and omitting gate structures above fins while retaining them alongside, which reduces gate capacitance and enhances switching speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device sizes are scaled down to increase functional density, then production efficiency increases and costs decrease, but manufacturing precision and alignment difficulty worsen
Solution Approach 1:
The gate structure is segmented into multiple portions (first gate portion, second gate portion, third gate portion) with different configurations relative to the fin. This segmentation allows each portion to be optimized independently for its specific function while maintaining overall device performance at scaled dimensions.
Solution Approach 2:
Different regions of the gate structure are given different qualities and configurations. The first gate portion wraps around the fin while the second and third portions are disposed alongside, creating local variations in gate control and capacitance that optimize both performance and manufacturability at scaled dimensions.
2Reliability
If gate structures are wrapped around fins to increase contact area, then gate control improves and short channel effects reduce, but manufacturing complexity and alignment difficulty increase
Solution Approach 1:
The gate structure is divided into multiple portions with different configurations. The first gate portion provides wraparound control while the second and third portions provide lateral control, allowing the device to achieve excellent gate control without requiring a complete wraparound structure which would be more complex to manufacture.
Solution Approach 2:
Instead of forming a complete wraparound gate structure, the invention inverts the approach by forming gate portions alongside the fin in addition to the wraparound portion. This inverted configuration achieves similar or better control with reduced manufacturing complexity.
3Reliability
If gate structures are retained above fins, then gate control is maximized, but gate capacitance increases and switching speed decreases
Solution Approach 1:
The gate structure implements local quality by having the first gate portion wrap around the fin for maximum control where needed, while the second and third gate portions are disposed alongside the fin at different heights. This creates local variations in gate capacitance that reduce overall capacitance while maintaining control in critical regions.
Solution Approach 2:
The invention adds a vertical dimension to the gate structure by disposing gate portions at different heights relative to the fin. The second gate portion is disposed above the fin at a first height and the third gate portion is disposed above the fin at a second height, creating a three-dimensional gate configuration that reduces capacitance while maintaining control.
Data Source
AI summary
Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.