FinFET Gate Spacer Tuning for Contact Area and Carrier Mobility
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing FinFET devices due to the complexity of forming gate structures with varying spacings, which affects the device's performance and efficiency, particularly in achieving optimal carrier mobility and reducing the distance between epitaxy structures and channel portions.
Innovation Solution
The process involves forming semiconductor fins on a substrate with varying dummy gate spacings, followed by an implantation process that increases the etching rate of gate spacers, allowing for the reduction of spacer thickness and subsequent formation of source/drain features with different widths, and ultimately replacing dummy gates with metal gate stacks, optimizing the gate-to-gate spacing and source/drain contact areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy gates with varying spacings are formed to optimize device performance, then carrier mobility and device speed are improved, but the manufacturing process complexity increases
Solution Approach 1:
The substrate is divided into first and second device regions with different dummy gate spacings. First dummy gates are formed with a first spacing and second dummy gates with a second spacing, allowing independent optimization of each region's carrier mobility and device speed characteristics without requiring a completely different manufacturing process for each region.
Solution Approach 2:
Different dummy gate spacings are applied to different device regions based on their specific performance requirements. The first device region uses a first spacing optimized for its characteristics, while the second device region uses a second spacing optimized for its characteristics, enabling local optimization of carrier mobility and device speed.
2Speed
If gate spacer thickness is reduced to decrease distance between epitaxy structures and channel, then device speed is improved, but manufacturing precision requirements increase
Solution Approach 1:
Gate spacers are formed with a preliminary thickness that is then selectively removed through etching processes. This preliminary formation allows for better process control and enables subsequent tuning of the final spacer thickness to achieve the optimal distance between epitaxy structures and channel portions while maintaining manufacturability.
Solution Approach 2:
The gate spacer thickness is adjusted as a variable parameter through selective etching processes. By controlling the etching conditions and duration, the final spacer thickness can be tuned to achieve the desired distance between epitaxy structures and channel portions, optimizing device speed while accounting for manufacturing capabilities.
3Reliability
If source/drain features with different widths are formed to optimize contact areas, then resistance is reduced, but device complexity increases
Solution Approach 1:
Source and drain features are formed with different widths in different device regions. First source/drain features have a first width optimized for the first device region, while second source/drain features have a second width optimized for the second device region. This enables local optimization of contact areas and resistance characteristics without requiring a completely different structure across all regions.
Solution Approach 2:
The source/drain structure is segmented into different width regions corresponding to different device regions. This segmentation allows each region's source/drain features to be independently optimized for their specific electrical characteristics and contact requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device performance by reducing the distance between epitaxy structures and the channel, improving carrier mobility and device speed, while also optimizing contact areas for reduced resistance, thus addressing the challenges of varying gate spacings and device efficiency.
Implementation Method 1
an implantation process that increases the etching rate of gate spacers
Data Source
AI summary
A device comprises a first transistor, a second transistor, a first contact, and a second contact. The first transistor comprises a first gate structure, first source/drain regions on opposite sides of the first gate structure, and first gate spacers spacing the first gate structure apart from the first source/drain regions. The second transistor comprises a second gate structure, second source/drain regions on opposite sides of the second gate structure, and second gate spacers spacing the second gate structure apart from the second source/drain regions. The first contact forms a first contact interface with one of the first source/drain regions. The second contact forms a second contact interface with one of the second source/drain regions. An area ratio of the first contact interface to top surface the first source/drain region is greater than an area ratio of the second contact interface to top surface of the second source/drain region.