FinFET Gate Spacer Doping for Lower Parasitic Capacitance
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Solution Overview
Problem
The scaling down of semiconductor integrated circuit manufacturing poses challenges in fabricating three-dimensional designs like FinFETs, particularly in achieving precise patterning and reducing parasitic capacitance to enhance device performance.
Innovation Solution
A manufacturing method for FinFETs involving the formation of fins on a semiconductor substrate, followed by the creation of isolation structures, stack structures, spacers, and source/drain regions, with a fluorine-doped spacer process to reduce dielectric constant and parasitic capacitance, and the subsequent formation of gate structures and interlayer dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional doping methods are used, then dopant distribution is achieved, but precise control of dopant placement on inner sidewalls is difficult
Solution Approach 1:
The patent applies tilted ion implantation at angles of 15-30 degrees relative to the normal of the inner sidewall surface. This angular approach introduces a dimensional change from perpendicular deposition, enabling dopants to be precisely embedded into the inner sidewalls of gate spacers while avoiding contamination of the gate electrode, thereby achieving precise dopant placement control
Solution Approach 2:
The patent performs selective doping only on the inner sidewalls of gate spacers adjacent to source/drain regions, rather than uniform doping across the entire structure. This localized approach concentrates dopant placement where needed to modulate carrier concentration in specific channel regions, improving manufacturing precision while maintaining process manageability
2Object-affected harmful factors
If spacer thickness is increased to reduce parasitic capacitance, then gate-to-contact capacitance decreases, but device area increases
Solution Approach 1:
The patent modifies the dielectric constant parameter of the gate spacer material by incorporating fluorinated silane compounds during deposition. This chemical parameter change reduces the dielectric constant of the spacer material, thereby decreasing gate-to-contact parasitic capacitance without requiring increased spacer thickness, thus avoiding device area expansion
Solution Approach 2:
The patent uses composite dielectric materials for gate spacers, combining silicon oxide with fluorinated components. This composite approach creates a material with lower effective dielectric constant than pure silicon oxide, reducing parasitic capacitance while maintaining the compact device geometry and minimizing area occupation
3Productivity
If three-dimensional FinFET structure is implemented, then functional density increases, but fabrication complexity increases
Solution Approach 1:
The patent performs preliminary formation of gate spacers with controlled thickness and material composition before FinFET patterning and doping steps. This preliminary preparation establishes a well-defined structural foundation that simplifies subsequent fabrication steps, enabling three-dimensional FinFET construction while managing overall fabrication complexity through staged process planning
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables improved carrier mobility and device performance by reducing gate-to-contact capacitance and enhancing the effective capacitance of FinFETs, leading to better ring oscillator speed and overall device efficiency.
Implementation Method 1
a doping process is performed to inner sidewalls of the spacer structure with a tilt angle ranging from about 0.5 degrees to 20 degrees
Implementation Method 2
A doping process is performed to inner sidewalls of the spacer structure with a tilt angle ranging from about 0.5 degrees to 20 degrees
Data Source
AI summary
Field effect transistor and manufacturing method thereof are disclosed. The field effect transistor includes a substrate, fins, a gate structure, a first spacer and a second spacer. The fins protrude from the substrate and extend in a first direction. The gate structure is disposed across and over the fins and extends in a second direction perpendicular to the first direction. The first spacer is disposed on sidewalls of the gate structure. The second spacer is disposed on the first spacer and surrounds the gate structure. The first spacer is fluorine-doped and includes fluorine dopants.