Layered FinFET Gate Spacer With Gas Gap for Lower RC Delay
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Solution Overview
Problem
Current multiple-gate finFET transistor manufacturing processes face challenges in reducing parasitic capacitance and RC time delay due to the limitations of existing dielectric materials and etching processes, which affect the performance and efficiency of semiconductor devices.
Innovation Solution
The implementation of a layered dielectric structure comprising a high-k first dielectric layer and a low-k porous second dielectric layer with different etch properties, along with a gap formation between these layers, reduces parasitic capacitance and enhances etching selectivity, thereby decreasing RC time delay. This structure includes a first dielectric layer with higher etch resistance, a second porous low-k dielectric layer, and a gap filled with gas, which separates the layers and reduces capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional dielectric structure is used, then the manufacturing process is simple, but parasitic capacitance is high and RC time delay increases
Solution Approach 1:
The dielectric structure is divided into multiple segments: a first dielectric layer with high etch resistance and a second dielectric layer with low etch resistance. This segmentation allows each layer to serve different functions - the first layer provides structural integrity and high capacitance blocking, while the second layer enables selective gap formation to reduce parasitic capacitance, thereby resolving the contradiction between structural simplicity and capacitance reduction.
Solution Approach 2:
Different regions of the dielectric structure are assigned different properties. The first dielectric layer has high etch resistance for structural stability, while the second dielectric layer has low etch resistance to allow gap formation in specific locations. This local differentiation of material properties enables targeted parasitic capacitance reduction without compromising overall structural integrity.
2Ease of manufacture
If dielectric layers with similar etch properties are used, then the manufacturing process is simpler, but etching selectivity is poor and gap formation is difficult
Solution Approach 1:
The etch resistance parameter is deliberately varied between the first and second dielectric layers. The first layer uses materials with high etch resistance (such as silicon nitride or silicon oxynitride), while the second layer uses materials with low etch resistance (such as spin-on-glass or porous low-k dielectric). This parameter differentiation enables selective etching of the second layer to form gaps, achieving high manufacturing precision in gap formation while maintaining relatively simple manufacturing processes.
3Device complexity
If a continuous dielectric layer is used, then the structure is simpler, but parasitic capacitance between gate and contact is high
Solution Approach 1:
A gap is extracted or removed from the continuous dielectric structure by selectively removing the second dielectric layer. This gap acts as an electrical isolation region that breaks the continuous dielectric path between the gate and contact, thereby reducing parasitic capacitance. The extraction of this dielectric portion creates a beneficial discontinuity that eliminates the harmful capacitive coupling while maintaining the overall structural simplicity through the use of only two dielectric layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The layered dielectric structure effectively decreases parasitic capacitance and RC time delay by utilizing the differences in etch properties and dielectric constants, improving the performance and efficiency of semiconductor devices.
Implementation Method 1
a first dielectric layer and a second dielectric layer with different etch properties
Implementation Method 2
removing at least a portion of the second dielectric layer such that a sidewall of the first dielectric layer is exposed... a gap filled with gas, which separates the layers and reduces capacitance
Data Source
AI summary
A method of forming a semiconductor device includes forming a gate structure on a semiconductor substrate. A gate spacer is formed adjacent to the gate structure. The gate spacer includes a first dielectric layer and a second dielectric layer on the first dielectric layer. A plasma treatment is performed to the second dielectric layer. After performing the plasma treatment, at least a portion of the second dielectric layer is removed such that a sidewall of the first dielectric layer is exposed. A dielectric cap is formed on the gate spacer.