FinFET Spacer Dielectric Treatment for Gate Isolation
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Solution Overview
Problem
In the manufacturing process of fin field effect transistors (Fin FETs), the removal of dummy gates can lead to narrowed spacer dielectric regions, resulting in gate-to-source/drain encroachment and poor isolation.
Innovation Solution
The process involves forming a dielectric etch back region and spacer elements, optimizing the height of the spacer dielectric region, and using a surface treatment process to improve immunity against etching solutions, thereby enhancing gate-to-source/drain isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If dummy gates are removed in the manufacturing process, then the device structure is simplified, but gate-to-source/drain isolation deteriorates and encroachment occurs
Solution Approach 1:
A surface treatment layer is formed on the spacer dielectric region before the dummy gate removal process. This preliminary action prepares the surface to resist encroachment during subsequent etching processes, preventing gate-to-source/drain isolation deterioration that would otherwise occur when dummy gates are removed.
Solution Approach 2:
The surface treatment layer acts as an intermediary between the spacer dielectric region and the etching solution. This intermediate layer provides the necessary resistance to encroachment during dummy gate removal, allowing the dummy gates to be removed while maintaining gate-to-source/drain isolation.
2Quantity of substance
If spacer dielectric region height is reduced, then device density increases, but immunity against etching solutions decreases
Solution Approach 1:
The surface treatment layer changes the chemical parameters of the spacer dielectric region surface, providing etching resistance without requiring increased height. This allows the spacer dielectric region to maintain reduced height for high device density while the surface treatment layer provides the necessary immunity against etching solutions.
Solution Approach 2:
The spacer dielectric region is combined with a surface treatment layer to create a composite structure. This composite provides both the reduced height needed for high device density and the etching resistance provided by the surface treatment layer, resolving the contradiction between density and immunity.
3Ease of manufacture
If conventional manufacturing processes are used, then process simplicity is maintained, but hot carrier degradation increases
Solution Approach 1:
The surface treatment layer is applied in advance to the spacer dielectric region before dummy gate removal and other processing steps. This preliminary protection prevents hot carrier degradation during manufacturing and operation, extending device lifetime while adding only one step to the manufacturing process.
Data Source
AI summary
A method of semiconductor fabrication includes forming a dielectric layer over a substrate. A dummy gate structure is formed on the dielectric layer, which defines a dummy gate dielectric region. A portion of the dielectric layer not included in the dummy gate dielectric region is etched to form a dielectric etch back region. A spacer element is formed on a portion of the dielectric etch back region, which abuts the dummy gate structure, and defines a spacer dielectric region A height of the dummy gate dielectric region is greater than the height of the spacer dielectric region. A recessed portion is formed in the substrate, over which a strained material is selectively grown to form a strained recessed region adjacent the spacer dielectric region. The dummy gate structure and the dummy gate dielectric region are removed. A gate electrode layer and a gate dielectric layer are formed.