FinFET Spacer Structure for Precise Etching and Low Capacitance
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Solution Overview
Problem
The challenge in manufacturing FinFETs lies in achieving precise control over the formation of fins and gate structures to enhance electrical control and carrier mobility, while existing methods face issues with etching selectivity and maintaining low gate-to-source/drain capacitance.
Innovation Solution
The manufacturing process involves forming a stack structure with a seal spacer and offset spacers using dielectric materials like SiCN and SiCON, followed by epitaxial growth of strained material portions to increase carrier mobility, and the use of high-k dielectric materials for improved gate performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar CMOS devices are used, then manufacturing is simpler, but electrical control over the channel is insufficient
Solution Approach 1:
The patent transitions from planar 2D channel structure to three-dimensional FinFET structure with vertical fins extending from the substrate. The gate electrode wraps around the fin structure in a U-shape, providing control from top, bottom, and sidewalls, thereby adding dimensional control authority over the channel while maintaining manufacturability through established semiconductor fabrication processes.
2Manufacturing precision
If etching processes are used to form fins and gates, then structural precision is improved, but etching selectivity becomes difficult to maintain
Solution Approach 1:
The patent introduces multiple dielectric layers with different etch selectivities as intermediaries during the formation process. These include a first dielectric layer with a first etch selectivity relative to the fin, a second dielectric layer with a second etch selectivity, and a third dielectric layer with a third etch selectivity. These intermediary layers enable selective etching of different structures at different stages, allowing precise fin and gate formation while maintaining manufacturing feasibility through selective removal of sacrificial and spacer materials.
3Productivity
If gate structures are made smaller to continue scaling, then device density is improved, but gate-to-source/drain capacitance increases
Solution Approach 1:
The FinFET structure extends the channel into the vertical dimension with fins rising from the substrate. This three-dimensional configuration increases the effective channel width and device density without proportionally increasing the gate-to-source/drain overlap area, thereby improving device density while controlling parasitic capacitance compared to planar scaling approaches.
Solution Approach 2:
The gate electrode is segmented into multiple portions that wrap around individual fins or fin groups. This segmentation allows independent optimization of gate control for each fin region and reduces the continuous overlap area between gate and source/drain, thereby lowering gate-to-source/drain capacitance while maintaining high device density through efficient use of vertical space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables better electrical control, increased carrier mobility, and reduced gate-to-source/drain capacitance, enhancing the performance of FinFETs by forming precise fin and gate structures.
Implementation Method 1
epitaxial growth of strained material portions
Data Source
AI summary
A fin-type field effect transistor including a substrate, insulators, a gate stack, a first spacer, a second spacer, and a third spacer is described. The substrate has fins thereon. The insulators are located over the substrate and between the fins. The gate stack is located over the fins and over the insulators. The first spacer is located over the sidewall of the gate stack. The second spacer is located over the first spacer. The first spacer and the second spacer includes carbon. The third spacer is located between the first spacer and the second spacer.