FinFET Spacer Fin Overlay Error Margin via Dimensional Adjustment
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Solution Overview
Problem
As semiconductor integrated circuits scale down, the reduced overlay error margin in the fin cut process becomes increasingly difficult to manage, particularly in the fabrication of fin field effect transistor (FinFET) devices, due to the shrinking space between spacer fins.
Innovation Solution
The method involves forming a substrate with specific layer structures, including a semiconductor layer, pad oxide, silicon nitride, and amorphous carbon layers, and using a dummy mandrel pattern to create spacer fins. By adjusting the dimensions of the hard mask patterns and spacer layers, the space between spacer fins is increased, enhancing the overlay error margin during the fin cut process. This is achieved through a series of deposition, etching, and patterning steps, including anisotropic etching and plasma etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the critical dimension is scaled down to increase functional density, then production efficiency is improved and costs are lowered, but the overlay error margin is reduced making the fin cut process increasingly difficult to manage
Solution Approach 1:
The fin cut process is divided into multiple sequential steps with intermediate spacer formation and removal. The first fin cut removes initial spacers, then a second spacer is formed and etched back, followed by a second fin cut. This segmentation allows each step to be performed with relaxed overlay requirements compared to a single-step cut, effectively managing the reduced overlay error margin at scaled dimensions
Solution Approach 2:
Dummy mandrel patterns are formed beforehand to define the initial spacer positions. These dummy mandrels serve as templates that pre-establish the geometric framework for subsequent spacer formation, ensuring that the actual fin structures will be positioned within acceptable overlay margins before the critical fin cut process begins
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The increased space between spacer fins improves the overlay error margin by approximately 20% at a pitch of 45 nm, allowing for more precise and efficient fin cut processes in semiconductor device fabrication.
Implementation Method 1
plasma etching processes
Implementation Method 2
anisotropic etching
Implementation Method 3
deposition, etching, and patterning steps, including anisotropic etching and plasma etching processes
Data Source
AI summary
A method includes receiving a substrate having an etch stop layer deposited over the substrate and a dummy mandrel layer deposited over the etch stop layer, forming a plurality of hard mask patterns using a hard mask layer deposited over the dummy mandrel layer, wherein the hard mask patterns includes a first dimension adjusted by a predetermined value, depositing a first spacer layer over the hard mask patterns, wherein a thickness of the first spacer layer is adjusted by the predetermined value, forming a plurality of spacer fins in the dummy mandrel layer, wherein the spacer fins include a second dimension, a first space, and a second space, performing a first fin cut process to remove at least one spacer fin, adjusting the second dimension to a target dimension, performing a second fin cut process, and forming a plurality of fin structures in the substrate by etching the spacer fins.