FinFET Spacer Structure for Low-Capacitance Source/Drain Scaling
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Solution Overview
Problem
The scaling down of MOSFETs in semiconductor devices leads to deterioration in operational properties, such as electric and reliability characteristics, due to technical limitations.
Innovation Solution
A semiconductor device is designed with an active pattern on a substrate, source/drain patterns, a channel pattern, a gate electrode, and spacers. The source/drain patterns include a body portion with a crystalline surface and a neck portion, where the crystalline surface is spaced apart from the uppermost portion of the fence portion of the spacer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOSFETs are scaled down to meet increasing demand for small pattern size, then device density and integration are improved, but operational properties and reliability characteristics deteriorate
Solution Approach 1:
The patent introduces a three-dimensional FinFET structure with vertical fins extending from the substrate, transitioning from planar two-dimensional channel to three-dimensional vertical channel. This dimensional change allows continued scaling of footprint area while maintaining effective channel length and improving device performance through increased gate control and surface area
Solution Approach 2:
The channel region is segmented into multiple vertical fins rather than a single planar channel. Each fin acts as an independent current path, allowing the total channel width to be distributed across multiple segments. This segmentation improves gate control over the channel and reduces short-channel effects while maintaining scalability
2Volume of moving object
If source/drain patterns are reduced in volume and width to improve device density, then parasitic capacitance decreases, but contact failures between adjacent patterns may occur
Solution Approach 1:
Spacer structures are introduced as intermediary elements between adjacent source/drain patterns and around the gate electrode. These spacers provide physical separation and electrical isolation, preventing unwanted contact and short circuits between adjacent devices while allowing the source/drain patterns to be closely spaced for high density
Solution Approach 2:
Thin film spacer layers are deposited conformally around the gate electrode and source/drain structures. These thin films provide effective electrical isolation with minimal volume, enabling close spacing of active elements while preventing contact failures through the insulating barrier provided by the spacer film
Data Source
AI summary
A semiconductor device includes an active pattern provided on a substrate, a source/drain pattern provided on the active pattern, a channel pattern configured to be connected to the source/drain pattern, a gate electrode configured to be extended in a first direction and to cross the channel pattern, and a first spacer provided on a side surface of the gate electrode. The first spacer includes a fence portion provided on a side surface of the active pattern and below the source/drain pattern. The source/drain pattern includes a body portion and a neck portion between the body portion and the active pattern. The body portion includes a crystalline surface configured to be slantingly extended from the neck portion. The crystalline surface is configured to be spaced apart from an uppermost portion of the fence portion.