FinFET Gate Spacer Voids for Lower Gate-to-Source Capacitance
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, they face challenges such as increased current leakage due to high capacitance between gate electrodes and source/drain regions, which existing technologies have not adequately addressed.
Innovation Solution
The formation of voids between gate electrodes and source/drain regions, filled with air or vacuum, reduces capacitance by using multiple gate spacers with different etch selectivities, allowing for the removal of one spacer to create these voids, thereby decreasing current leakage in FinFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but current leakage increases due to high capacitance between gate electrodes and source/drain regions
Solution Approach 1:
The patent removes the second gate spacer material selectively to create voids between the gate electrode and source/drain regions. This extraction of unnecessary material reduces the capacitance-forming dielectric volume, thereby reducing current leakage while maintaining high integration density achieved through small feature sizes
Solution Approach 2:
The patent introduces voids (porous spaces filled with air or vacuum) between the gate electrode and source/drain regions. These porous structures have significantly lower permittivity compared to solid dielectric materials, reducing the capacitance and associated current leakage while preserving the compact device structure
2Loss of energy
If voids are formed between gate electrodes and source/drain regions to reduce capacitance, then current leakage decreases, but device structure becomes more complex
Solution Approach 1:
The patent uses multiple gate spacer layers with different etch selectivities, dividing the spacer formation into sequential steps. The first gate spacer is deposited and patterned, then the second gate spacer is deposited and selectively removed. This segmentation allows precise control over void formation while maintaining overall process manageability
Solution Approach 2:
The patent changes the etch selectivity parameter by using different dielectric materials for the first and second gate spacers. This parameter change enables selective removal of the second spacer to create voids, achieving capacitance reduction through a controlled process rather than complex structural modifications
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces current leakage in FinFETs by increasing the relative permittivity of the space between gate electrodes and source/drain contacts, enhancing device performance and integration density.
Implementation Method 1
The capacitance between the gate electrodes and source/drain contacts of the FinFET may thus be reduced, thereby reducing current leakage in the FinFET
Data Source
AI summary
In an embodiment, a device includes: a first fin extending from a substrate; a gate stack disposed on the first fin; a source/drain region disposed in the first fin; a contact etch stop layer (CESL) disposed over the source/drain region; a gate spacer extending along a side of the gate stack; and a dielectric plug disposed between the CESL and the gate spacer, where the dielectric plug, the CESL, the gate spacer, and the source/drain region collectively define a void physically separating the gate stack from the source/drain region.