FinFET Split Gate Memory Cell Leakage Control
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Solution Overview
Problem
Conventional split gate non-volatile memory cells face challenges in scaling due to issues such as insufficient and non-uniform doping, ballistic electron transport, complex integration with high K metal gate processes, increased capacitive coupling, and sub-threshold leakage, which affect read currents and access times.
Innovation Solution
A non-volatile memory cell design featuring two serially connected transistors with FinFet architecture, where one transistor has a polysilicon floating gate between silicon fins, allowing for improved control of cell leakage and read current scaling, using a split gate architecture with separate control and erase gates, and optimized floating gate dimensions for enhanced reliability and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional planar floating gate memory cells are scaled down, then device density increases, but read currents decrease and access times increase
Solution Approach 1:
The patent transitions from planar 2D channel structure to 3D FinFET structure, where the channel is formed as a vertical fin extending from the substrate. This dimensional change increases the effective channel width without increasing the footprint area, thereby maintaining read current levels while achieving higher device density through vertical scaling.
Solution Approach 2:
The patent embeds the floating gate structure within the FinFET architecture, where the floating gate is positioned between the control gate and the channel fin. This nested configuration allows the memory cell to maintain its non-volatile functionality while benefiting from the enhanced current drive of the FinFET structure.
2Area of stationary object
If floating gate dimensions are reduced for scaling, then device area decreases, but capacitive coupling between neighboring floating gates increases
Solution Approach 1:
The patent introduces isolation structures including oxide regions and nitride spacers that segment and electrically isolate neighboring floating gates. These isolation elements are positioned between adjacent memory cells, creating electrical barriers that reduce capacitive coupling while allowing the floating gate dimensions to be reduced for scaling.
3Ease of manufacture
If conventional doping techniques are used in ultra-thin polysilicon, then manufacturing process remains simple, but doping uniformity and sufficiency deteriorate
Solution Approach 1:
The patent performs doping operations at multiple stages during the fabrication process, including pre-floating gate doping and post-floating gate doping. This multi-stage doping approach ensures sufficient and uniform doping of the ultra-thin polysilicon floating gate by preparing the substrate beforehand and completing doping after floating gate formation, thereby achieving manufacturing precision without excessive process complexity.
4Productivity
If FinFET structure is adopted to increase channel width, then current flow increases, but device footprint increases
Solution Approach 1:
The patent utilizes vertical fins extending from the substrate surface to create three-dimensional channel structures. This vertical dimensionality allows the channel width to be increased through the fin height and perimeter without increasing the horizontal footprint, thereby maintaining high current flow capability while achieving high device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively addresses scalability challenges, reduces cross-talk, and improves read current density and leakage control, enabling efficient programming and read operations while maintaining reasonable physical dimensions and integrating with advanced CMOS flows.
Implementation Method 1
a tunnel dielectric and a floating gate are formed adjacent to the first fin with the tunnel dielectric between the floating gate and the first fin
Implementation Method 2
a control gate is formed adjacent to the interpoly dielectric such that the interpoly dielectric is between the floating gate and the control gate
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3A~3B
AI summary
A non- volatile memory cell formed on a semiconductor substrate having an upper surface with an upwardly extending fin with opposing first and second side surfaces. First and second electrodes are in electrical contact with first and second portions of the fin. A channel region of the fin includes portions of the first and second side surfaces that extend between the first and second portions of the fin. A floating gate extends along the first side surface of a first portion of the channel region, where no portion of the floating gate extends along the second side surface. A word line gate extends along the first and second side surfaces of a second portion of the channel region. A control gate is disposed over the floating gate. An erase gate has a first portion disposed laterally adjacent to the floating gate and a second portion disposed vertically over the floating gate.