FinFET Split Gate Non-Volatile Memory Cell Formation
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Solution Overview
Problem
Existing technologies face challenges in simultaneously forming FinFET type logic devices and three-gate, split-gate non-volatile memory cells on the same semiconductor substrate without adversely affecting each other's processing steps.
Innovation Solution
A method involving the formation of silicon fins with side surfaces, followed by polysilicon deposition to create floating, erase, and word line gates that wrap around these fins, with a metal gate replacement for enhanced channel region performance, allowing for the contemporaneous formation of logic and memory devices on a shared substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If FinFET structures are used to increase effective channel width, then current flow increases, but lateral footprint increases
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional FinFET structures where the gate wraps around the fin on multiple sides. This dimensional change allows the effective channel width to be increased by utilizing the vertical fin structure and multi-side gate coverage, thereby increasing current flow without proportionally increasing the lateral footprint on the semiconductor substrate
2Ease of manufacture
If polysilicon deposition is used to form gates for both memory and logic devices, then processing steps can be shared, but subsequent processing steps may adversely affect previously fabricated devices
Solution Approach 1:
The patent divides the semiconductor substrate into distinct memory cell regions and logic device regions. Different FinFET structures are formed in each region - three-gate FinFETs for memory cells and single-gate FinFETs for logic devices. This segmentation allows each region to be optimized independently while sharing common processing steps like polysilicon deposition, thereby maintaining ease of manufacture while protecting device performance through region-specific structure optimization
Solution Approach 2:
The patent applies different gate configurations to different regions: three-gate FinFET structures with floating gate, erase gate, and word line gate are used in memory cell regions, while single-gate FinFET structures are used in logic device regions. This local quality approach ensures that each region has the optimal structure for its function, preventing adverse effects from uniform processing on device performance
3Adaptability or versatility
If three-gate FinFET memory cells and FinFET logic devices are formed on the same substrate, then integration is achieved, but processing complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming isolation structures, recesses, and region definitions before forming the different FinFET structures. Memory cell regions are prepared with appropriate isolation and recess configurations prior to polysilicon deposition, and logic device regions are prepared with their own specific structures. This preliminary preparation simplifies subsequent processing steps and reduces overall processing complexity while achieving high-level device integration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the effective channel region area without increasing lateral size, enabling smaller device scaling, simplifies processing, and reduces the impact on CMOS baseline fabrication, while improving conductivity and erase efficiency.
Implementation Method 1
performing a first implantation to form a first source region in the first silicon fin; performing a second implantation to form a first drain region in the first silicon fin and to form a second source region and a second drain region in the second silicon fin
Implementation Method 2
forming a floating gate disposed over and insulated from a first portion of the first channel region using a first polysilicon deposition, wherein the floating gate wraps around the top and side surfaces of the first silicon fin; forming an erase gate disposed over and insulated from the first source region, and a word line gate disposed over and insulated from a second portion of the first channel region, and a dummy gate disposed over and insulated from the second channel region, using a second polysilicon deposition
Data Source
AI summary
A method of forming a device with a silicon substrate having upwardly extending first and second fins. A first implantation forms a first source region in the first silicon fin. A second implantation forms a first drain region in the first silicon fin, and second source and drain regions in the second silicon fin. A first channel region extends between the first source and drain regions. A second channel region extends between the second source and drain regions. A first polysilicon deposition is used to form a floating gate that wraps around a first portion of the first channel region. A second polysilicon deposition is used to form an erase gate wrapping around first source region, a word line gate wrapping around a second portion of the first channel region, and a dummy gate wrapping around the second channel region. The dummy gate is replaced with a metal gate.