FinFET Split Gate Memory Cell with Silicon Nanocrystals
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Solution Overview
Problem
Existing split gate memory devices face challenges in optimizing memory cell configuration and efficiency, particularly in terms of space utilization and power consumption during programming operations.
Innovation Solution
The implementation of FinFETs with a split gate configuration, utilizing silicon nanocrystals for charge storage and employing Source Side Injection (SSI) programming techniques, allows for independent control gate structures adjacent to each sidewall of semiconductor fins, enabling more compact memory cell arrays and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional split gate memory devices are used, then memory cell configuration is achieved, but space utilization and power consumption during programming operations are suboptimal
Solution Approach 1:
The gate structure is segmented into two independent gates: a control gate and a select gate. This segmentation allows independent control of charge injection and storage, enabling the memory cell to achieve compact configuration while reducing programming power consumption through selective gate control during programming operations
Solution Approach 2:
The invention transitions from planar memory cell configuration to three-dimensional FinFET structure with vertical fins extending from the substrate. This dimensional change enables improved space utilization by stacking memory cells vertically, while the split gate configuration along the fin structure reduces programming power through localized charge control
2Area of stationary object
If FinFET with split gate configuration is implemented, then compact memory cell array is achieved, but manufacturing complexity increases
Solution Approach 1:
The gate is divided into control gate and select gate segments that can be formed using separate deposition and patterning steps. This segmentation enables the compact FinFET structure to be manufactured through modular processing, where each gate segment is independently formed and then integrated, reducing overall manufacturing complexity
Solution Approach 2:
The control gate and select gate structures are nested within the FinFET architecture, with gates positioned along the vertical fin structure. This nesting approach consolidates multiple functional elements into a compact three-dimensional arrangement, achieving space efficiency while managing manufacturing complexity through integrated formation processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a more compact memory cell array with lower power requirements during programming, leveraging SSI techniques for faster and efficient data storage, while maintaining the benefits of FinFET transistors.
Implementation Method 1
a charge storage structure having a first portion adjacent a second portion of the first sidewall and adjacent to a second portion of the channel region along the first sidewall
Implementation Method 2
a control gate structure having a first portion adjacent to the first portion of the charge storage structure
Implementation Method 3
employing Source Side Injection (SSI) programming techniques
Data Source
AI summary
A memory cell is implemented using a semiconductor fin in which the channel region is along a sidewall of the fin between source and drains regions. One portion of the channel region has a select gate adjacent to it and another other portion has the control gate adjacent to it with a charge storage structure there between. In some embodiments, independent control gate structures are located adjacent opposite sidewalls of the fin so as to implement two memory cells.