FinFET Split Gate Memory Cells with Intersecting Fins
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Solution Overview
Problem
As semiconductor device geometries shrink, the channel region area in split gate non-volatile memory cells decreases, leading to reduced current flow and the need for more sensitive sense amplifiers, which is not efficiently addressed by existing Fin-FET structures that use floating gates in stacked configurations or other complex memory cell designs.
Innovation Solution
A memory device with Fin-FET split gate type memory cells featuring a floating gate, control gate, select gate, and erase gate extending along the side and top surfaces of fins, allowing increased channel region surface area without increasing semiconductor real estate, and a method of forming these cells on a semiconductor substrate with intersecting fins to enhance current flow and reduce footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If device geometries are shrunk to reduce memory cell footprint, then semiconductor real estate is reduced, but channel region area and current flow decrease
Solution Approach 1:
The patent transitions from a planar channel structure to a three-dimensional FinFET structure with vertical fins extending from the substrate. This dimensional change allows the channel to utilize vertical space rather than only horizontal space, increasing channel surface area while reducing the horizontal footprint of the memory cell. The fin structure provides channel regions on multiple surfaces (top and sidewalls) that contribute to current flow without increasing the planar area occupied by the device.
2Area of moving object
If channel region area is reduced due to geometry scaling, then current flow decreases, but sense amplifier sensitivity requirements increase
Solution Approach 1:
By creating vertical fins that extend upward from the substrate, the patent increases the channel surface area available for current flow. The FinFET structure provides channel regions on the top surface and sidewalls of the fin, effectively multiplying the channel area without increasing the planar footprint. This maintains adequate current flow levels even as device geometries are scaled down.
3Area of moving object
If Fin-FET structure is used to increase channel width, then current flow increases, but device complexity increases
Solution Approach 1:
The patent divides the channel into multiple segments formed by vertical fins, with each fin providing its own channel region on the top and sidewalls. The floating gate is segmented to wrap around multiple fins, with each segment controlling a portion of the channel. This segmentation approach increases effective channel width while maintaining a relatively simple overall structure that can be fabricated using standard FinFET processes.
Data Source
AI summary
A memory device including a plurality of upwardly extending fins in a semiconductor substrate upper surface. A memory cell is formed on a first of the fins, and includes spaced apart source and drain regions in the first fin, with a channel region extending along top and opposing side surfaces of the first fin between the source and drain regions. A floating gate extends along a first portion of the channel region. A select gate extends along a second portion of the channel region. A control gate extends along the floating gate. An erase gate extends along the source region. A second of the fins has a length that extends in a first direction which is perpendicular to a second direction in which a length of the first fin extends. The source region is formed in the first fin at an intersection of the first and second fins.