FinFET SRAM Beta Ratio via Orthogonal Mask Patterning
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Solution Overview
Problem
Conventional SRAM device fabrication techniques face challenges in achieving an improved beta ratio, leading to performance degradation due to inadvertent removal of adjacent fins and rounding of fin portions, which affects the stability and precision of the SRAM cell.
Innovation Solution
The use of at least two orthogonal mask layers during fin structure patterning allows for selective removal and encapsulation of fin portions within a gate structure, enhancing the beta ratio by creating squared edges and electrical isolation of pass-gate transistors, thereby improving the stability of the SRAM device without increasing cell size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional single mask layer patterning is used, then fabrication process is simple, but fin structures are inadvertently removed and edges become rounded, degrading manufacturing precision
Solution Approach 1:
The patent divides the patterning process into multiple stages using at least two mask layers. The first mask layer patterns the fin structures, and the second mask layer refines the pass-gate transistor definition by removing portions of fins and creating squared edges. This segmentation allows each mask layer to perform a specific function, achieving high precision without the drawbacks of a single complex mask layer.
Solution Approach 2:
The first mask layer performs preliminary patterning of the fin structures before the second mask layer refines the geometry. By preparing the fin structures in advance with the first mask layer, the second mask layer can focus on precise edge definition and fin removal, achieving high manufacturing precision through sequential preliminary actions.
2Reliability
If equal number of pull-down and pass-gate devices are used, then cell size is minimized, but beta ratio equals 1 causing access disturb and reduced stability
Solution Approach 1:
The patent applies local quality by selectively removing portions of fin structures only in the pass-gate transistor regions using the second mask layer. This creates different geometries in different parts of the cell: pass-gate transistors have reduced fin areas while pull-down transistors maintain full fin areas. This local modification increases the beta ratio without requiring overall cell expansion.
Solution Approach 2:
The patent changes the geometric parameters of the fin structures by removing portions selectively. This modifies the drive current characteristics of the pass-gate transistors relative to pull-down transistors, thereby changing the beta ratio from 1 to a higher value. The parameter change is achieved through controlled fin removal rather than increasing overall cell dimensions.
3Ease of manufacture
If conventional patterning without orthogonal mask layers is used, then process steps are reduced, but fin edges become rounded causing epitaxial growth issues
Solution Approach 1:
The patent introduces a second dimension to the patterning process by using orthogonal mask layers. The first mask layer patterns in one orientation, and the second mask layer patterns in a perpendicular orientation. This dimensional approach creates squared edges by intersecting pattern lines, preventing the rounded edges that occur with conventional single-direction patterning while adding manageable process complexity.
Data Source
AI summary
Fabrication method for a semiconductor memory device and structure are provided, which includes: providing at least two mask layers over a pair of fin structures extended above a substrate, wherein a first mask layer of the at least two mask layers is orthogonal to a second mask layer of the at least two mask layers; and patterning the pair of fin structures to define a pass-gate transistor, wherein the first mask layer facilitates removing of a portion of a first fin structure of the pair of fin structures to define a first pass-gate fin portion of the pass-gate transistor, and the second mask layer protects a second fin structure of the pair of fin structures to define a second pass-gate fin portion of the pass-gate transistor.