FinFET SRAM Cell Layout for Sub-22nm Alignment Precision
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional SRAM cell layouts face challenges in sub-22 nm geometries due to alignment issues, jog or corner-related mismatches, and orthogonal lithography, which affect yield and functionality.
Innovation Solution
The method involves forming FinFET-based SRAM cells using a unidirectional, jogless process with iso-dimensional structures, where FinFETs are aligned with shared contacts, reducing cell size and bit line capacitance by aligning gates with shared contacts, and using a two-mask process for contact formation to improve proximity and reduce misalignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional SRAM cell layouts with jogs or notches are used, then the layout can be formed using standard fabrication processes, but alignment challenges in sub-22 nm geometries lead to pull-down device mismatch and reduced yield
Solution Approach 1:
The SRAM cell layout is segmented into distinct regions with shared contacts positioned at specific locations, allowing independent optimization of alignment for each segment. The cell is divided such that pull-up and pull-down devices are spatially separated around the shared contacts, enabling precise alignment control for each device type without interference from jogs or notches.
Solution Approach 2:
Instead of forming contacts first and then aligning gates to them (conventional approach), the invention inverts the sequence by precisely forming gates first and then aligning shared contacts to the gates. This inversion allows the gate structure, which can be formed with higher precision, to serve as the reference for contact alignment, thereby improving overall alignment precision and eliminating device mismatch.
2Manufacturing precision
If orthogonal lithography is used for shared contact formation, then contacts can be formed in two directions, but this reduces control of critical dimensions and increases process complexity
Solution Approach 1:
The invention extracts the orthogonal lithography step from the fabrication process, eliminating the need for two-directional contact formation. By forming all shared contacts in a single lithography direction aligned with the gates, the process removes the complexity of orthogonal alignment while maintaining precise critical dimension control through unidirectional patterning.
Solution Approach 2:
The shared contacts serve multiple functions: they provide electrical connection for both pull-up and pull-down devices, act as alignment references for subsequent processing steps, and enable compact cell layout. This multi-functionality is achieved through a simplified unidirectional lithography process that forms all contacts in one direction, reducing process complexity while maintaining versatility.
3Reliability
If larger SRAM cell area is used, then device matching can be improved, but cell size increases and bit line capacitance increases leading to reduced read delay performance
Solution Approach 1:
The SRAM cell layout employs a nested arrangement where pull-up and pull-down devices are interleaved around shared contacts in a compact configuration. This nesting allows devices to be closely spaced without overlapping, achieving excellent matching through proximity while maintaining a minimized cell area that reduces bit line capacitance and improves read delay performance.
Solution Approach 2:
The invention optimizes the geometric parameters of the cell layout, specifically the spacing and positioning of shared contacts relative to gates. By changing these parameters to create a compact nested arrangement, the cell area is minimized while device matching is maintained through precise geometric relationships, thereby reducing bit line capacitance and improving read speed.
Data Source
AI summary
A semiconductor device is provided that includes a first inverter having a first p-channel FinFET and a first n-channel FinFET each coupled to a first shared contact forming a first cell node and having a first common gate. A second inverter is included having a second p-channel FinFET and a second n-channel FINFET each coupled to a second shared contact forming a second cell node and having a second common gate aligned with the first shared contact of the first inverter forming a latch circuit. Additionally, a pair of FinFET passgates are included each having a drain contact respectively coupled the first and second cell nodes and a source contact connected to one of a complementary bit line. Finally, a word line is connected to a gate contact of each of the pair of FinFET passgates to provide a static random access memory cell.