FinFET SRAM Structure for Stable Data Retention Without Refresh
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Solution Overview
Problem
Current SRAM technologies face challenges in maintaining data stability without refresh cycles, as they rely on dynamic memory that requires power to retain data, limiting their reliability and speed compared to static RAM.
Innovation Solution
The implementation of six-transistor (6T) SRAM cells using fin field effect transistors (FinFETs) with cross-coupled inverters and pass-gate transistors, which maintain complementary values at storage nodes indefinitely as long as power is supplied, eliminating the need for refresh cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dynamic RAM is used for memory storage, then the device complexity is reduced, but the reliability and speed are worsened due to the need for refresh cycles
Solution Approach 1:
The patent segments the memory cell into six distinct transistors (two pull-up, two pull-down, two pass-gate transistors) arranged in a specific configuration. This segmentation allows each transistor to perform a dedicated function, enabling stable data storage without refresh cycles while maintaining a manageable structural organization through the systematic arrangement of these segmented components
Solution Approach 2:
The patent creates a multi-functional memory cell structure where the same six-transistor configuration serves multiple purposes: data storage, data retention without refresh, and integration with standard CMOS fabrication processes. The cross-coupled inverter configuration provides both storage functionality and automatic data maintenance, eliminating the need for separate refresh circuitry
2Duration of action of stationary object
If refresh cycles are implemented in memory, then data retention is improved, but the speed and efficiency are worsened due to continuous refresh operations
Solution Approach 1:
The patent implements continuous data retention through the cross-coupled inverter configuration where the two inverters continuously reinforce each other's output states. The pull-up and pull-down transistors maintain complementary voltage levels at the storage nodes indefinitely, providing uninterrupted data retention without periodic refresh operations, thus maintaining both long duration and high speed simultaneously
Solution Approach 2:
The memory cell structure is self-maintaining through its cross-coupled configuration. The inverters and transistors automatically sustain the stored data state through their inherent feedback mechanism, requiring no external refresh signals or control circuitry. The system serves itself by continuously maintaining its own state as long as power is supplied, eliminating the productivity loss associated with external refresh operations
Data Source
AI summary
A device includes a semiconductor substrate, a semiconductor fin, a gate structure, a first source/drain epitaxy structure, a second source/drain epitaxy structure, a first dielectric fin sidewall structure, a second dielectric fin sidewall structure. The semiconductor fin is over the semiconductor substrate. The semiconductor fin includes a channel portion and recessed portions on opposite sides of the channel portion. The gate structure is over the channel portion of the semiconductor fin. The first source/drain epitaxy structure and the second source/drain epitaxy structure are over the recessed portions of the semiconductor fin, respectively. The first source/drain epitaxy structure has a round surface. The first dielectric fin sidewall structure and the second dielectric fin sidewall structure are on opposite sides of the first source/drain epitaxy structure. The round surface of the first source/drain epitaxy structure is directly above the first dielectric fin sidewall structure.