FinFET SRAM Cell Gate Structure for RC Delay Reduction
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Solution Overview
Problem
The increasing complexity and down-scaling of Static Random Access Memory (SRAM) cells lead to higher sheet resistance in metal lines, resulting in increased RC delay, which hinders improvements in read and write speed.
Innovation Solution
The implementation of fin field-effect transistors (FinFETs) with specific gate structures and dielectric materials, along with conductive line patterns and dummy gate electrode patterns, to enhance the performance and reliability of SRAM cells by reducing short channel leakage and improving turn-on current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If SRAM cells are down-scaled to increase functional density, then the number of interconnected devices per chip area increases, but the sheet resistance of metal lines increases and RC delay increases
Solution Approach 1:
The patent transitions from planar metal line connections to three-dimensional vertical FinFET structures. The FinFET channel extends vertically from the substrate surface, creating a third dimension for current flow. This dimensional change allows maintaining low resistance despite reduced horizontal dimensions, as the vertical channel provides efficient carrier transport path independent of metal line sheet resistance.
Solution Approach 2:
The patent changes the physical parameters of the transistor structure by introducing FinFET geometry with controlled fin height, width, and aspect ratio. By adjusting these dimensional parameters, the device achieves optimized on-current and threshold voltage characteristics. The fin height and width are specifically tuned to maintain low resistance while enabling aggressive scaling, thereby improving speed despite reduced feature sizes.
2Productivity
If SRAM cells are down-scaled, then functional density increases, but short channel leakage increases
Solution Approach 1:
The FinFET structure introduces a vertical dimension to the channel, transforming it from a two-dimensional planar structure to a three-dimensional folded channel. This vertical extension increases the effective channel length without increasing the horizontal footprint, providing better gate control over the channel and suppressing short channel effects and leakage currents while maintaining small device area for high functional density.
Solution Approach 2:
The patent employs composite material structures including high-k dielectric gate insulators combined with metal gate electrodes, and selectively doped semiconductor regions. The high-k dielectric layer provides superior electrical isolation and gate control, reducing off-state leakage. The composite structure of doped source/drain regions with the undoped fin channel creates potential barriers that suppress carrier leakage, enabling dense scaling while maintaining low short channel effects.
Data Source
AI summary
A static random access memory (SRAM) cell and a SRAM cell structure are provided. The SRAM cell includes a first pull-down transistor, a first pull-up transistor, a second pull-down transistor, a second pull-up transistor, a first conductive line pattern and a second conductive line pattern. A first gate electrode pattern of the first pull-down transistor and a second gate electrode pattern of the first pull-up transistor are physically separated from each other and electrically connected to the first conductive line pattern. The second inverter includes a second pull-down transistor, a second pull-up transistor and a second conductive line pattern. A third gate electrode pattern of the second pull-down transistor and a fourth gate electrode pattern of the second pull-up transistor are physically separated from each other and electrically connected to the second conductive line pattern.