FinFET SRAM Logic Gate Alignment for Reduced Ion Implantation
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Solution Overview
Problem
Conventional SRAM circuits require four ion implantation processes to form source/drain regions, increasing manufacturing costs due to the perpendicular routing directions of gate electrodes and active areas in control logic circuits.
Innovation Solution
All active transistors in memory cells and logic circuits are designed as FinFETs with gate electrodes aligned along the same longitudinal direction, reducing the number of ion implantation processes to two, parallel to the gate electrodes, thereby simplifying and cost-reducing the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional SRAM circuits use perpendicular routing directions of gate electrodes and active areas in control logic circuits, then the circuit functionality is achieved, but the number of ion implantation processes increases to four, increasing manufacturing costs
Solution Approach 1:
The patent merges the routing directions of gate electrodes and active areas to be parallel in control logic circuits, combining what were previously perpendicular orientations. This alignment allows all transistors (both in memory cells and control logic) to be formed using the same ion implantation process direction, reducing the total number of ion implantation processes from four to two, thereby lowering manufacturing costs.
2Productivity
If all active transistors use gate electrodes arranged along the same longitudinal direction, then the number of ion implantation processes is reduced to two, but the design and routing constraints increase
Solution Approach 1:
The patent creates a universal routing architecture where gate electrodes in both memory cells and control logic circuits are arranged along the same longitudinal direction. This universal orientation allows a single ion implantation process configuration to serve multiple transistor types and circuit functions, improving manufacturing efficiency by reducing the number of process steps from four to two ion implantation processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces manufacturing costs by minimizing the number of ion implantation steps required, enhancing the efficiency and cost-effectiveness of integrated circuit production while maintaining operational performance.
Implementation Method 1
All active transistors of all memory cells of the first memory array and all active transistors of the logic circuit are Fin field effect transistors (FinFETs) and have gate electrodes arranged along a first longitudinal direction
Implementation Method 2
Conventional SRAM circuits require four ion implantation processes to form source/drain regions
Data Source
AI summary
An integrated circuit including a first memory array and a logic circuit coupled with the first memory array. All active transistors of all memory cells of the first memory array and all active transistors of the logic circuit are Fin field effect transistors (FinFETs) and have gate electrodes arranged along a direction a first longitudinal direction.