FinFET IC Structure for SRAM Density and Interconnect Complexity
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Solution Overview
Problem
Current integrated circuit (IC) structures, particularly SRAM cells, face challenges in reducing size and increasing density, which limits the storage capacity and increases manufacturing costs per bit.
Innovation Solution
The proposed IC structure includes vertically-oriented semiconductor fins and gates with a unique configuration that allows for direct electrical connections between gates and conductive regions, enabling reduced size and enhanced connectivity for SRAM cells through the use of multiple semiconductor fins and insulating layers, along with specific fabrication methods to form trenches and contacts for electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional horizontal transistor layouts are used, then manufacturing processes are simpler, but device area is larger and density is lower
Solution Approach 1:
The patent transitions from conventional horizontal planar transistor layouts to vertically-oriented FinFET structures that extend in the vertical dimension. This dimensional change allows multiple transistors to be stacked and connected vertically, significantly reducing the footprint area while maintaining functional complexity through three-dimensional gate wrapping and vertical channel formation.
Solution Approach 2:
The patent implements nested structures where gates wrap around fins in multiple dimensions, and where complex interconnect structures are embedded within vertical trenches. The FinFET gate structure itself nests around the vertical fin, and additional gate layers can be stacked, creating a nested arrangement that packs more functionality into less area.
2Productivity
If vertically-oriented FinFET structures are used, then device density is increased, but electrical connection complexity between structures increases
Solution Approach 1:
The patent segments electrical connections into distinct vertical and horizontal components. Vertical connections are achieved through dedicated contact structures extending into trenches between fins, while horizontal connections use conductive regions at the base. This segmentation allows independent optimization of each connection type and simplifies the overall interconnect architecture despite the vertical orientation.
Solution Approach 2:
The patent introduces intermediate conductive regions and contact structures that mediate electrical connections between vertically-oriented fins and horizontal interconnects. These intermediary elements bridge the vertical and horizontal dimensions, providing low-resistance pathways without requiring complex direct connections between all vertical structures.
3Quantity of substance
If more transistors are integrated per unit area, then storage capacity increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary actions in the manufacturing process by first forming the vertical fin structures with controlled orientation before depositing the gate materials. The fin structures are pre-patterned and etched with precise vertical alignment, and the gate is then conformally deposited to wrap around the fins. This sequential preliminary structuring ensures that high-density integration achieves the required precision without requiring all steps to be performed with ultra-precise alignment simultaneously.
Data Source
AI summary
Embodiments of the present disclosure provide an integrated circuit (IC) structure and methods of electrically connecting multiple IC structures. An IC structure according to embodiments of the present disclosure can include: a first conductive region; a second conductive region laterally separated from the first conductive region; a first vertically-oriented semiconductor fin formed over and contacting the first conductive region; a second vertically-oriented semiconductor fin formed over and contacting the second conductive region; and a first gate contacting each of the first vertically-oriented semiconductor fin and the second conductive region, wherein the first gate includes: a substantially horizontal section contacting the first vertically-oriented semiconductor fin, and a substantially vertical section contacting the second conductive region.