FinFET Stack Gate Memory Scaling Below 120 nm
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Solution Overview
Problem
Existing stack gate memory technologies face limitations in scaling below 120 nm due to short channel effects, significant current loss, and reliability issues, with a maximum current of less than 20 μA and a small read margin, making further scaling difficult and unreliable.
Innovation Solution
A method for forming a FinFET stack gate memory involving nitride film formation, stripping, floating gate structure creation, oxide-nitride-oxide layer deposition, and control gate structure formation, which includes a shallow trench isolation structure, tunnel oxide, and polysilicon layers to enhance channel width and current reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional stack gate memory is scaled below 120 nm, then device density is improved, but short channel effects cause punch-through and hot carrier injection leading to reliability degradation
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional FinFET stack gate structures, utilizing vertical stacking to achieve higher device density while maintaining effective channel control. The FinFET architecture provides wrap-around gate control that suppresses short channel effects, enabling reliable operation at scaled dimensions below 120 nm while achieving the required density improvement.
Solution Approach 2:
The patent employs composite material structures including high-k dielectric materials combined with metal gate materials, and multi-layer stack gate configurations. These composite structures enable better electrical control of the channel while reducing leakage currents, thereby maintaining reliability during scaling. The high-k metal gate (HKMG) combination provides superior gate control compared to conventional silicon dioxide/silicon nitride stacks.
2Area of stationary object
If effective channel width is reduced below 80 nm, then device area is reduced, but maximum current is limited to less than 20 μA causing small read margin
Solution Approach 1:
The FinFET stack gate structure utilizes the vertical dimension to increase effective channel width without increasing planar device footprint. By stacking multiple fins vertically, the effective channel width is expanded in the vertical direction while maintaining a compact lateral footprint, thereby achieving both area reduction and sufficient current drive capability for adequate read margin.
Solution Approach 2:
The channel is segmented into multiple parallel fins within the stack gate structure. Each fin contributes to the total current, and by having multiple fins in parallel, the effective channel width is increased while maintaining a compact device area. This segmentation allows the current to be distributed across multiple pathways, achieving the required read margin.
3Ease of manufacture
If conventional stacking methods are used, then manufacturing process is simple, but channel width control precision is insufficient leading to current loss
Solution Approach 1:
The patent employs preliminary patterning steps including mandrel formation and spacer deposition before final fin patterning. The spacer thickness, controlled by atomic layer deposition (ALD), precisely defines the fin width and spacing. This preliminary action sequence enables precise channel width control while maintaining a manageable manufacturing process through standard semiconductor fabrication techniques.
Solution Approach 2:
The patent utilizes atomic layer deposition (ALD) to precisely control oxide layer thicknesses, which in turn control the fin dimensions and spacing. By adjusting deposition parameters such as cycle number and precursor flow rates, the channel width is precisely controlled at the nanometer scale. This parameter control through ALD enables manufacturing precision while keeping the overall process compatible with conventional CMOS fabrication.
Data Source
AI summary
A method of forming a FinFET stack gate memory includes a nitride film forming step, a nitride film is formed on a memory cell area with a shallow trench isolation (STI) structure; a stripping step, a portion of the nitride film is stripped, the other portion of the nitride film is remained at the STI structure, and a STI oxide is disposed in the STI structure; a floating gate (FG) structure forming step, a tunnel oxide is disposed, and a first polysilicon is disposed to form a FG structure; an oxide-nitride-oxide (ONO) layer disposing step, a portion of the STI oxide is stripped, and an ONO layer is disposed; a removing step, a portion of the ONO layer is removed; a control gate (CG) structure forming step, a portion of the FG structure is removed, and a second polysilicon is disposed to form a CG structure.