FinFET Stepped Gate Profile for Voltage Threshold Uniformity
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Solution Overview
Problem
Current methods for forming FinFET devices fail to provide uniform voltage thresholds in the channel region, limiting their performance and efficiency.
Innovation Solution
A method for fabricating FinFET devices involving the formation of a fin structure with shallow trench isolation, multiple insulation layers, and a gate structure with a longitudinal stepped profile, which enhances the effective gate length and improves voltage threshold uniformity by minimizing gate cornering and allowing better LDD region push into the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional FinFET fabrication methods are used, then manufacturing process is simpler, but voltage threshold uniformity in the channel region deteriorates
Solution Approach 1:
The gate structure is segmented into multiple regions with different heights, creating a stepped profile along the longitudinal axis. This segmentation allows different portions of the gate to provide different levels of control over the channel, enabling uniform voltage threshold across the channel region while maintaining a manageable fabrication process through sequential deposition and planarization steps
Solution Approach 2:
The gate structure transitions from a conventional two-dimensional planar configuration to a three-dimensional stepped profile with varying heights along the longitudinal axis. This dimensional change enables enhanced control over the channel region by providing multiple gate heights that can independently influence different portions of the channel, thereby achieving uniform voltage threshold without excessive manufacturing complexity
2Reliability
If gate structure with stepped profile is formed, then effective gate length increases and voltage threshold uniformity improves, but manufacturing process complexity increases
Solution Approach 1:
Different insulation layers are applied to different portions of the fin structure based on local requirements. The first insulation layer is formed on portions of the fin structure that require enhanced isolation, while the second insulation layer is formed in other regions. This localized approach allows the stepped gate profile to achieve improved voltage threshold uniformity and extended effective gate length without uniformly increasing complexity across the entire device structure
Data Source
AI summary
A FinFET device and a method for fabricating a FinFET device are disclosed. An exemplary method of fabricating a FINFET device includes providing a substrate including a fin structure including a plurality of fins and shallow trench isolation (STI) features between each fin of the fin structure. A first gate structure is formed over the fin structure. First gate spacers are formed on sidewalls of the first gate structure. The first gate spacers are removed while leaving portions of the first gate spacers within corners where the fin structure and the first gate structure meet. Second gate spacers are formed on sidewalls of the first gate structure. A dielectric layer is formed over the fin structure, the first gate structure, and the second gate spacers. The first gate structure and the portions of the first gate spacers are removed, thereby exposing sidewalls of the second gate spacers. A second gate structure is formed over the fin structure in a region where the first gate structure and the portions of the first gate spacers have been removed.