FinFET STI Recess Etch Tuning for Uniform SiGe Channel Heights
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Solution Overview
Problem
The variation in channel heights of silicon germanium (SiGe) channels in FinFET transistors due to different fin densities leads to uneven etching rates during the recess etch of shallow trench isolation, causing exposure mismatches and resulting in DC penalty and AC degradation.
Innovation Solution
A selective implantation process is performed prior to recess etching dielectric materials around semiconductor fin structures to alter their etching rates, ensuring different fin heights match corresponding channel heights across regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If recess etch is performed on shallow trench isolation around semiconductor fin structures with different fin densities, then isolation structures are formed, but channel height mismatches occur causing exposure mismatches and DC/AC penalties
Solution Approach 1:
A planarization layer is formed over the semiconductor fin structures before the recess etch process. This preliminary action creates a uniform surface that compensates for the different fin heights, ensuring that the recess etch exposes the fin structures at matching channels regardless of their initial height differences, thereby preventing exposure mismatches and associated DC/AC penalties
Solution Approach 2:
The planarization layer acts as an intermediary between the fin structures of different heights and the recess etch process. It provides a uniform reference surface that mediates the etching process, allowing the etch to proceed to a consistent depth that matches all fin channels despite variations in fin structure heights
2Productivity
If fin density varies across different regions, then more components can be integrated, but uneven etching rates occur during recess etch
Solution Approach 1:
The planarization layer is formed with locally adaptive thickness to compensate for regional variations in fin density and height. In regions with lower fin density and shorter fins, the planarization layer is thicker, while in regions with higher fin density and taller fins, it is thinner, ensuring uniform exposure across all regions during recess etch
Solution Approach 2:
The planarization process changes the surface topology parameter by creating a non-uniform thickness profile that inversely compensates for the fin height variations caused by different fin densities, transforming the uneven surface into a uniform exposure surface for the recess etch process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively addresses channel height mismatches, improving drain-induced barrier lowering (DIBL) and reducing AC/DC penalties in p-type devices with SiGe channels by ensuring uniform fin and channel heights.
Implementation Method 1
A selective implantation process is performed prior to recess etching dielectric materials around semiconductor fin structures to alter their etching rates
Data Source
AI summary
Embodiments of the present disclosure provides a solution to address any issues caused by non-uniform channel heights across a substrate. Particularly, an isolation layer is selectively implanted to alter etching rate of the isolation layer around semiconductor fin structures prior to STI recess.