FinFET Fabrication Using Annealed STI and Semiconductor Stacks
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Solution Overview
Problem
As semiconductor devices shrink below 30 nm, severe short channel effects and thin gate dielectric lead to increased leakage current and off-state power consumption, limiting their functionality, and traditional silicon technology faces challenges in improving carrier mobility and gate control.
Innovation Solution
A method is developed to form fin-shaped structures on a substrate, followed by a dielectric layer transformation into shallow trench isolation (STI) through an anneal process, and then constructing a semiconductor stack structure within the trench using alternating layers of different materials to enhance device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is reduced below 30 nm to achieve higher device density, then device density is improved, but leakage current increases due to severe short channel effects
Solution Approach 1:
The patent transitions from planar transistors to three-dimensional FinFET structures, utilizing vertical channel formation to improve gate control. The fin-shaped structure extends into the third dimension (vertical direction), allowing better electrostatic control over the channel while maintaining small footprint area, thus achieving high device density without suffering from severe short channel effects that plague scaled planar devices.
Solution Approach 2:
The patent employs high-k dielectric materials combined with metal gate structures to replace traditional silicon dioxide gate dielectrics. This composite material approach enables thinner effective gate control with reduced leakage current, as the high-k material provides superior dielectric strength while the metal gate offers better work function control and lower off-state power consumption.
2Reliability
If gate dielectric is thinned to improve gate control, then gate control is improved, but off-state power consumption increases
Solution Approach 1:
The patent changes the dielectric constant parameter by introducing high-k materials (such as hafnium oxide, tantalum oxide) with dielectric constants significantly higher than silicon dioxide. This parameter change allows achieving the same electrical control with physically thicker dielectric layers, thereby reducing direct tunneling leakage while maintaining effective gate control over the channel.
Solution Approach 2:
The patent combines high-k dielectric layers with metal gate materials to create a composite gate structure that provides both superior dielectric properties for leakage reduction and adjustable work function for optimal threshold voltage control, thereby achieving low off-state power consumption while maintaining strong gate control.
3Ease of manufacture
If traditional silicon technology is used to simplify manufacturing, then manufacturing complexity is reduced, but carrier mobility and gate control cannot be improved
Solution Approach 1:
The patent employs composite material structures including high-k dielectric layers, metal gate electrodes, and selectively doped semiconductor regions. These composite structures enable enhanced carrier mobility through improved electrostatic control and reduced scattering, while the fabrication processes build upon existing CMOS manufacturing techniques, maintaining reasonable manufacturing complexity.
Solution Approach 2:
The patent utilizes vertical channel structures (FinFETs) that extend into the third dimension, providing superior gate control over the channel compared to planar devices. This dimensional transition improves carrier mobility through better electrostatic control and reduced short channel effects, while the fabrication process uses adapted versions of standard semiconductor manufacturing techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces germanium diffusion during STI formation, improving the quality and performance of fin-shaped structures by forming the stack structure on top, thereby addressing leakage current issues and enhancing carrier mobility and gate control.
Implementation Method 1
performing an anneal process to transform the dielectric layer into a shallow trench isolation (STI)
Data Source
AI summary
A method for fabricating a semiconductor device includes the steps of first forming a fin-shaped structure on a substrate, forming a dielectric layer surrounding the fin-shaped structure, performing an anneal process to transform the dielectric layer into a shallow trench isolation (STI), removing the fin-shaped structure to form a trench, and forming a stack structure in the trench. Preferably, the stack structure includes a first semiconductor layer on the fin-shaped structure and a second semiconductor layer on the first semiconductor layer and the first semiconductor layer and the second semiconductor layer include different materials.