FinFET Storage Device for DRAM Cell Scaling
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Solution Overview
Problem
Conventional DRAM devices face challenges in providing sufficient capacitance and maintaining good off-state leakage and on-state characteristics, especially as they shrink in size, leading to poor performance characteristics such as retention time, access time, and reliability issues, particularly in capacitor-less designs like 1T/0C DRAM cells.
Innovation Solution
The use of a partially depleted FinFET with a wrapped-around gate structure for a 1T/0C DRAM cell, employing charge generation methods like impact ionization, band-to-band tunneling, and channel-initiated secondary hot electrons to enhance carrier generation efficiency, and incorporating features like high-k gate oxides and rare-earth elements to improve data retention and programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DRAM devices are physically shrunk in size, then device integration density is improved, but capacitance sufficiency and transistor performance deteriorate
Solution Approach 1:
The patent transitions from planar 2D device architecture to three-dimensional FinFET structure with wrapped-around gate. The FinFET body extends vertically from the substrate surface, creating a third dimension for charge storage. This vertical dimension increases the effective active area and charge capacity without increasing the planar footprint, thereby maintaining integration density while improving capacitance and transistor performance.
Solution Approach 2:
The gate structure wraps around the FinFET body in a nested configuration, with the gate enclosing the channel region from multiple sides. This nested gate structure provides superior electrostatic control over the channel and enhances carrier generation efficiency through improved electric field distribution, addressing the performance deterioration issue while maintaining compact device size.
2Length of moving object
If planar SOI devices are physically reduced in size, then device scaling is improved, but charge storage capacity deteriorates
Solution Approach 1:
The FinFET structure introduces a vertical dimension to charge storage by extending the semiconductor body upward from the substrate. The wrapped gate encompasses this vertical structure, creating a three-dimensional charge storage region. This allows charge storage capacity to be increased through vertical scaling rather than planar scaling, enabling device size reduction while maintaining or improving charge capacity.
3Ease of operation
If 1T/0C DRAM cells use impact ionization for carrier generation, then write operation is achieved, but device reliability and efficiency deteriorate at higher temperatures
Solution Approach 1:
The patent modifies the physical parameters of the FinFET structure, including the gate wrap-around geometry, oxide thickness, and doping profiles, to enhance carrier generation efficiency. These parameter changes improve the quantum yield of carrier generation through impact ionization, maintaining write operation capability while improving reliability and efficiency at higher temperatures by optimizing the electric field distribution and carrier multiplication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves data retention, reduces power consumption, and enhances reliability by effectively scaling down DRAM cells while maintaining charge capacity, offering superior control over sub-threshold and linear operating regions with a low threshold voltage.
Implementation Method 1
In a 1T/0C DRAM cell, carriers are generated in the substrate bulk to write a '1'
Implementation Method 2
carriers are pulled out from the substrate bulk to write a '0'
Implementation Method 3
employing charge generation methods like impact ionization, band-to-band tunneling, and channel-initiated secondary hot electrons to enhance carrier generation efficiency
Data Source
AI summary
A memory device and method of making the memory device. The memory device comprises a storage transistor at a surface of a substrate. The storage transistor comprises a body portion between first and second source/drain regions, wherein the source/drain regions are regions of a first conductivity type. The storage transistor also comprises a gate structure that wraps at least partially around the body portion in at least two spatial planes. A bit line is connected to the first source/drain region and a word line is connected to the gate structure.