FinFET Gate Structure with Strain Engineering
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing the size and increasing the complexity of memory cells, particularly in the development of Fin field effect transistors (FINFETs), where existing technologies struggle to effectively control the channel from three sides and achieve desired strain stress for enhanced mobility.
Innovation Solution
The formation of FinFETs with a gate structure orthogonal to fin-channel bodies, incorporating strain structures and epitaxial regions to provide compressive or tensile stress, and using a multilayer gate dielectric structure to enhance electron and hole mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional planar transistors are used, then manufacturing is simpler, but channel control from multiple sides is insufficient
Solution Approach 1:
The patent transitions from planar 2D channel control to 3D FinFET structure where the gate wraps around the channel in three dimensions, providing control from top and sidewalls. This dimensional change enables superior electrostatic control and drive current while maintaining scalability for advanced technology nodes.
Solution Approach 2:
The channel is segmented into multiple fins arranged in parallel, each fin providing an independent current path. This segmentation allows the total channel width to be distributed across multiple narrow fins, improving gate control while maintaining high drive current capability.
2Productivity
If transistor size is reduced to increase density, then more devices fit on chip, but strain stress control becomes difficult
Solution Approach 1:
The patent introduces localized strain through selectively positioned stressor structures adjacent to specific fin regions. Different fins or channel regions can have different strain characteristics (tensile or compressive) applied locally, enabling optimized carrier mobility in high-density configurations where uniform strain control is challenging.
Solution Approach 2:
The channel structure employs composite materials including SiGe source/drain regions combined with silicon channel fins, or III-V semiconductor materials such as GaAs or InGaAs for the channel. These composite material structures provide inherent strain and high mobility while maintaining small device dimensions for high density.
3Speed
If gate dielectric thickness is reduced to increase drive current, then transistor speed improves, but leakage current increases
Solution Approach 1:
The patent transitions from conventional thin silicon oxide gate dielectrics to high-k dielectric materials such as hafnium oxide, barium oxide, or lanthanum oxide. The high dielectric constant (k-value) of these materials enables achieving the same capacitance and drive current with a physically thicker dielectric layer, thereby reducing gate leakage current and power consumption while maintaining fast switching speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for improved control of the channel and increased mobility, enabling the fabrication of smaller and more complex integrated circuits with enhanced performance.
Implementation Method 1
incorporating strain structures and epitaxial regions to provide compressive or tensile stress, and using a multilayer gate dielectric structure to enhance electron and hole mobility
Data Source
AI summary
An integrated circuit including a plurality of Fin field effect transistors (FINFETs) is provided. The integrated circuit includes a plurality of fin-channel bodies over a substrate. The fin-channel bodies include a first fin-channel body and a second fin-channel body. A gate structure is disposed over the fin-channel bodies. At least one first source/drain (S/D) region of a first FINFET is adjacent the first fin-channel body. At least one second source/drain (S/D) region of a second FINFET is adjacent the second fin-channel body. The at least one first S/D region is electrically coupled with the at least one second S/D region. The at least one first and second S/D regions are substantially free from including any fin structure.