FinFET Strain Induction via Shared Epitaxial Growth
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing complex and efficient semiconductor devices, particularly in creating both n-type and p-type FinFETs with high drive currents and small footprints, where existing methods require separate epitaxial growth processes for each type, increasing complexity and time.
Innovation Solution
A method involving a shared epitaxial growth process for n-type and p-type FinFETs, where channel regions are strained using a strain relaxed buffer layer and annealing to induce tensile and compressive stress respectively, allowing both types to be fabricated using the same material stack in a single round of epitaxial growth, with a patterned thermal mask for selective annealing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate epitaxial growth processes are used for n-type and p-type FinFETs, then each device type can be optimized independently, but manufacturing complexity and time increase
Solution Approach 1:
The patent combines the fabrication of n-type and p-type FinFETs into a single shared epitaxial growth process. Both device types are formed simultaneously in the same reaction chamber using the same material stack (including strain relaxed buffer layers), eliminating the need for separate growth processes and reducing manufacturing complexity while maintaining device optimization capabilities through selective strain induction.
Solution Approach 2:
The shared epitaxial growth process serves multiple functions: it grows the channel regions for both n-type and p-type FinFETs, forms the strain relaxed buffer layers for both device types, and enables subsequent selective strain induction through patterned thermal masking. This multi-functional approach replaces what would traditionally require separate specialized processes.
2Manufacturing precision
If separate epitaxial growth processes are used for n-type and p-type FinFETs, then each device type can be optimized independently, but manufacturing time increases
Solution Approach 1:
The patent implements continuous useful action by performing the epitaxial growth of both n-type and p-type FinFET channel regions in a single uninterrupted process. The shared growth process continuously deposits material for both device types simultaneously, and the subsequent selective annealing step continuously induces strain in the appropriate regions without interrupting the manufacturing flow, thereby minimizing total manufacturing time.
Solution Approach 2:
The strain relaxed buffer layers are grown preliminarily during the shared epitaxial growth process before the FinFET channel regions. This preliminary formation of strained buffer layers enables subsequent selective strain induction during device operation without requiring additional growth steps, reducing overall manufacturing time while maintaining device optimization.
3Reliability
If strain relaxed buffer layers are used for both n-type and p-type FinFETs, then high drive currents are achieved, but process complexity increases
Solution Approach 1:
The patent applies local quality by using a patterned thermal mask during the annealing process. The mask selectively exposes only the n-type FinFET channel regions to the annealing treatment that induces tensile strain, while protecting p-type regions. This localized strain induction achieves high drive currents for each device type without requiring different buffer layer structures, thereby maintaining process simplicity.
Solution Approach 2:
The patent utilizes parameter changes by controlling the annealing temperature and duration to induce specific strain states in the buffer layers. By adjusting these thermal parameters and combining them with selective masking, the process achieves the desired tensile strain for n-type devices and compressive strain for p-type devices from the same buffer layer material, avoiding the need for different material compositions or complex multi-step strain induction processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the simultaneous fabrication of n-type and p-type FinFETs with reduced manufacturing time and complexity, achieving efficient strain induction and defect reduction, while maintaining high drive currents and small footprints.
Implementation Method 1
channel regions are strained using a strain relaxed buffer layer and annealing to induce tensile and compressive stress respectively
Implementation Method 2
performing an annealing process, thereby reversing strain on the first epitaxial layer of the first fin
Data Source
AI summary
A semiconductor device and a method of forming the same are disclosed. The device comprises a semiconductor substrate comprised of a first semiconductor material and having a plurality of isolation features, thereby defining a first active region and a second active region; a first fin semiconductor feature comprised of a second semiconductor material and formed in the first active region; and a second fin semiconductor feature comprised of a second semiconductor material and formed in the second active region. The first fin semiconductor feature is tensile strained and the second fin semiconductor feature is compressively strained.