FinFET Embedded Source-Drain Strain and Inner Oxide Spacer Design
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Solution Overview
Problem
Conventional FinFET fabrication techniques face challenges in maintaining high carrier mobility and reducing parasitic capacitance as devices shrink in size, with existing methods compromising fin channel quality and increasing parasitic capacitance.
Innovation Solution
The technique involves forming bulk-like embedded source/drain regions with enhanced strain using materials like eSiGe for pFETs and eSi:C for nFETs, and using low-temperature selective oxidation to create inner oxide spacers between the gate and source/drain regions, while forming fins with improved epitaxy quality to maintain strain and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional FinFET fabrication techniques are used to minimize device size, then device scaling is achieved, but parasitic capacitance increases and carrier mobility decreases
Solution Approach 1:
The patent extracts the gate electrode material from direct contact with the source/drain regions by introducing an inner oxide spacer layer between them. This separation removes the source of parasitic capacitance (the gate-stack overlap with source/drain) while maintaining the necessary electrical functionality, thereby reducing harmful capacitive coupling effects in scaled devices
Solution Approach 2:
An inner oxide spacer is introduced as an intermediary layer between the gate electrode and source/drain regions. This mediator physically separates components that would otherwise be in direct contact, reducing parasitic capacitance while still allowing the structure to function as intended in miniaturized FinFET devices
2Volume of moving object
If conventional FinFET fabrication techniques are used to minimize device size, then device scaling is achieved, but carrier mobility deteriorates
Solution Approach 1:
The patent applies different material compositions to different regions: the inner oxide spacer is formed with specific oxidation conditions tailored to the local requirements near the source/drain regions, while the gate electrode and channel regions maintain their optimized structures. This localized material optimization preserves carrier mobility in the channel while enabling size reduction
Solution Approach 2:
The oxidation parameters (temperature, time, atmosphere) are carefully controlled and optimized to form the inner oxide spacer with specific properties. By changing these process parameters, the patent achieves the desired balance between reducing parasitic capacitance and maintaining fin channel quality for high carrier mobility in scaled devices
3Object-generated harmful factors
If inner oxide spacers are formed using conventional oxidation methods, then parasitic capacitance is reduced, but fin channel quality deteriorates
Solution Approach 1:
The inner oxide spacer is formed through a preliminary oxidation step performed at a specific stage in the fabrication process, before final gate electrode deposition or adjustment. This preliminary action establishes the spacer structure early, allowing subsequent processes to be optimized for fin channel quality without compromising the capacitance reduction benefit
Solution Approach 2:
The oxidation temperature and duration are precisely controlled to form the inner oxide spacer with optimal thickness and composition. By adjusting these parameters, the patent achieves sufficient spacer formation to reduce parasitic capacitance while avoiding excessive oxidation that would damage fin channel quality and epitaxial integrity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances strain for improved carrier mobility and reduces parasitic capacitance, maintaining high device performance and efficiency without compromising fin channel quality.
Implementation Method 1
embedded source/drain regions with enhanced strain
Implementation Method 2
low-temperature selective oxidation to create inner oxide spacers
Data Source
AI summary
A method of forming a semiconductor structure includes forming a substrate, the substrate having a first portion with a first height and second recessed portions with a second height less than the first height. The method also includes forming embedded source/drain regions disposed over top surfaces of the second recessed portions of the substrate, and forming one or more fins from a portion of the substrate disposed between the embedded source/drain regions, the one or more fins providing channels for fin field-effect transistors (FinFETs). The method further includes forming a gate stack disposed over the one or more fins, and forming inner oxide spacers disposed between the gate stack and the source/drain regions.