FinFET Source/Drain Strain Layout for Sub-7nm Mobility Gains
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Solution Overview
Problem
Conventional strain boosters for fin-based field effect transistors (FETs) are reaching their limit, making it difficult to further enhance transistor mobility in sub-seven nanometer process nodes, which is necessary for continuous performance improvement in advanced logic complementary metal oxide semiconductor (CMOS) scaling.
Innovation Solution
The implementation of fin-based FETs with strained source/drain regions, where different stressor materials are used in the source/drain regions to enhance driver current and performance, involving a method that includes etching trenches and filling them with specific stressor materials, followed by the deposition of a metal gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional strain boosters are used in fin-based FETs, then device performance is maintained at current levels, but transistor mobility cannot be further enhanced in sub-seven nanometer process nodes
Solution Approach 1:
The patent applies different stressor materials to different regions: compressive stressor material in the source region and tensile stressor material in the drain region. This local differentiation optimizes carrier mobility specifically in the channel region while managing heat and current characteristics in respective regions, enabling continued performance improvement in sub-7nm nodes where conventional uniform strain boosters have reached their limit.
Solution Approach 2:
The patent employs composite material structures by combining different stressor materials (compressive and tensile) within the same device architecture. This composite approach allows simultaneous optimization of multiple parameters including mobility, current drive, and power characteristics, providing the adaptability needed for advanced logic CMOS scaling.
2Productivity
If device geometries are reduced to increase functional density, then production efficiency increases and costs decrease, but processing complexity increases
Solution Approach 1:
The patent segments the source/drain structure into distinct regions with different stressor materials applied to source and drain respectively. This segmentation allows independent optimization of each region's characteristics while maintaining overall device functionality, enabling scaling to smaller geometries without proportionally increasing processing complexity.
Solution Approach 2:
The patent changes material parameters by introducing different stressor materials with specific mechanical properties (compressive vs. tensile stress) to optimize device performance at scaled dimensions. This parameter adjustment enables continued performance improvement as geometries are reduced, offsetting the increased processing complexity through material-based solutions rather than geometric complexity.
3Power
If different stressor materials are used in source and drain regions, then driver current and performance are enhanced, but manufacturing process complexity increases
Solution Approach 1:
The patent applies stressor materials during the epitaxial growth process before final device fabrication steps. By establishing the differential stress structure early in the manufacturing sequence, subsequent processing steps can proceed with standard techniques, reducing overall manufacturing complexity despite the advanced device requirements.
Solution Approach 2:
The epitaxial growth process automatically creates the differential stress structure through controlled material deposition with inherent stress characteristics. This self-organizing process reduces the need for additional complex manufacturing steps to introduce strain, as the stressor materials are integrated during the fundamental device formation process itself.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor mobility and performance by applying targeted strain to the source/drain regions, addressing the limitations of conventional strain boosters and improving the performance-power-area (PPA) characteristics of fin-based devices.
Implementation Method 1
a first vertical structure on the substrate and comprising a source/drain region having a first stressor material; a second vertical structure on the substrate and comprising a drain/source region having a second stressor material different from the first stressor material
Data Source
AI summary
A field effect transistor (FET) is described. The FET includes a substrate, having a first vertical structure on the substrate, including a source/drain region having a first stressor material. The FET also includes a second vertical structure on the substrate and including a drain/source region having a second stressor material different from the first stressor material. The FET further includes a metal gate on the first vertical structure and on the second vertical structure.