FinFET Device Strained Layer Integration via Cladding
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Solution Overview
Problem
The integration of alternative semiconductor materials with silicon substrates in FinFET devices is hindered by lattice constant mismatches, leading to defects and limited formation of stable, fully-strained layers, which complicates the manufacturing of CMOS-based integrated circuits with enhanced performance and reliability.
Innovation Solution
The method involves forming PMOS and NMOS FinFET devices by creating fins with a lower substrate portion made of silicon and an upper portion of a different semiconductor material, followed by epitaxial growth of a semiconductor material cladding on the NMOS fin, using techniques such as 'gate-first' or 'replacement gate' methods, to enhance performance and reduce defect formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If alternative semiconductor materials are integrated with silicon substrates in FinFET devices, then device performance is improved, but lattice constant mismatches lead to defect formation and limited stable layer formation
Solution Approach 1:
The patent introduces strained relaxed buffer (SRB) layers as intermediary structures between the alternative semiconductor material and the silicon substrate. These SRB layers act as mediators that accommodate the lattice constant mismatch, preventing defect propagation to the active device regions while enabling the integration of high-performance alternative materials.
Solution Approach 2:
The patent segments the fin structure into multiple functional regions: a lower substrate portion made of silicon and an upper portion made of alternative semiconductor material. This segmentation allows each region to be optimized independently, with the silicon substrate providing mechanical support and the alternative material providing enhanced device performance.
2Reliability
If separate SRB layers are formed for NMOS and PMOS devices, then each device type can be optimized, but manufacturing complexity increases
Solution Approach 1:
The patent merges the SRB layer formation process by using a common SRB layer structure that serves both NMOS and PMOS devices. This unified approach eliminates the need for separate SRB layers for each device type, reducing manufacturing complexity while maintaining optimized performance for both device types through selective epitaxial growth and masking techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of fully-strained, defect-free semiconductor materials, improving the performance and reliability of FinFET devices by reducing leakage current and enhancing drive current capabilities, while also simplifying the manufacturing process by eliminating the need for separate SRB layers for NMOS and PMOS devices.
Implementation Method 1
epitaxial growth of a semiconductor material cladding on the NMOS fin
Data Source
AI summary
One illustrative method disclosed herein includes, among other things, forming first and second fins, respectively, for a PMOS device and an NMOS device, each of the first and second fins comprising a lower substrate fin portion made of the substrate material and an upper fin portion that is made of a second semiconductor material that is different from the substrate material, exposing at least a portion of the upper fin portion of both the first and second fins, masking the PMOS device and forming a semiconductor material cladding on the exposed upper portion of the second fin for the NMOS device, wherein the semiconductor material cladding is a different semiconductor material than that of the second semiconductor material. The method also including forming gate structures for the PMOS FinFET device and the NMOS FinFET device.